Wade Fife
fd87d4cf30
This adds support for different widths on each port and adds the ability to disable routes within the crossbar. Both of these features allow for FPGA resource savings. These features are controlled by the new parameters PORT_WIDTHS and ENABLED_PATHS. Unused routes will have the associated logic removed. A new testbench adds support for testing different port widths and disabled routes. It also adds more rigrous testing of the crossbar. Original-commit: 18bf81d91055b68765c44ca86a2cbcfa9704c749
55 lines
1.7 KiB
Makefile
55 lines
1.7 KiB
Makefile
#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = kintex7
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PART_ID = xc7k410t/ffg900/-2
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(AXI_SRCS) \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = chdr_crossbar_nxn_all_tb
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SIM_SRCS = \
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$(abspath chdr_crossbar_nxn_tb.sv) \
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$(abspath chdr_crossbar_nxn_all_tb.sv) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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