Wade Fife
fd87d4cf30
This adds support for different widths on each port and adds the ability to disable routes within the crossbar. Both of these features allow for FPGA resource savings. These features are controlled by the new parameters PORT_WIDTHS and ENABLED_PATHS. Unused routes will have the associated logic removed. A new testbench adds support for testing different port widths and disabled routes. It also adds more rigrous testing of the crossbar. Original-commit: 18bf81d91055b68765c44ca86a2cbcfa9704c749
692 lines
32 KiB
Verilog
692 lines
32 KiB
Verilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_crossbar_nxn
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//
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// Description:
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//
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// This module implements a full-bandwidth NxN crossbar with N input and
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// output ports for CHDR traffic. It supports multiple optimization
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// strategies for performance, area and timing trade-offs. It uses AXI-Stream
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// for all of its links. The crossbar has a dynamic routing table based on a
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// Content Addressable Memory (CAM). The SID is used to determine the
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// destination of a packet and the routing table contains a re-programmable
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// SID to crossbar port mapping. The table is programmed using special route
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// config packets on the data input ports or using an optional management
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// port.
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//
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// The topology, routing algorithms and the router architecture is described
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// in README.pdf in this directory.
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//
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// This crossbar also supports multiple port sizes. By default, each port
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// will be PORT_W bits wide. This can be changed using the CHDR_WIDTHS
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// parameter. This parameter allows the CHDR width of each port to be
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// specified. When using multiple CHDR widths, the PORT_W parameter should be
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// the size of the widest port. The CHDR_W value reported by the management
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// port will be the value specified for that port in CHDR_WIDTHS.
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//
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// Parameters:
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//
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// PORT_W : Width of the AXI-Stream data buses s_axis and m_axis. If
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// using multiple port widths, this should be set to the
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// width of the widest port.
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// NPORTS : Number of ports to instantiate.
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// CHDR_WIDTHS : Descending array of NUM_PORT integers representing the
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// width of each crossbar port. The width of port n is given
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// by CHDR_WIDTHS[(N+1)*32-1 : N*32].
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// ROUTES : Descending array representing which crossbar routes to
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// enable. This is an NPORTS*NPORTS-bit array where bit
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// [NPORTS*A + B] corresponds to the path from input port A
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// to output port B. A '1' indicates the logic for that route
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// is included. All routes are enabled by default.
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// EN_ROUTE_FIFO : Set to 1 to include a FIFO on all routes going from a wide
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// port to a narrow port. This may improve performance when a
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// single wide input port streams to multiple narrow output
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// ports by buffering the input data while it's resized for
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// the slower output port. This helps to avoid congestion on
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// the input port.
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// EN_ROUTE_GATE : Set to 1 to include a packet gate on all routes going from
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// a narrow port to a wide port. This may improve performance
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// when multiple narrow input ports stream to a single wide
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// output port by removing idle transfer cycles caused by the
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// slower rate of the narrow input port. This helps to avoid
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// congestion on the output port.
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// DEFAULT_PORT : The fail-safe port to forward a packet to if SID mapping
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// is missing.
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// BYTE_MTU : log2 of the max packet size in bytes.
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// ROUTE_TBL_SIZE: log2 of the number of mappings that the routing table can
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// hold at any time. Mapping values are maintained in a FIFO
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// fashion.
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// MUX_ALLOC : Algorithm to allocate the egress MUX. Possible values:
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// * "PRIO": Priority based. Lower port numbers have a
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// higher priority
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// * "ROUND-ROBIN": Round robin input port allocation
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// OPTIMIZE : Optimization strategy for performance vs area vs timing
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// trade-offs. Possible values:
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// * "AREA": Attempt to minimize area at the cost of
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// performance (throughput) and/or timing.
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// * "PERFORMANCE": Attempt to maximize performance at the
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// cost of area and/or timing.
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// * "TIMING": Attempt to maximize Fmax at the cost of area
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// and/or performance.
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// NPORTS_MGMT : Number of ports with management endpoint. The first
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// NPORTS_MGMT ports will have the management port
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// instantiated.
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// EXT_RTCFG_PORT: Enable a side-channel AXI-Stream management port to
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// configure the routing table.
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//
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// CHDR_WIDTHS Bit Mapping Example (4x4):
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//
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// Port #: 3 2 1 0
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// ↓ ↓ ↓ ↓
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// {32'd64, 32'd64, 32'd64, 32'd64}
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//
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// ROUTES Bit Mapping Example (4x4):
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//
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// Output Port: 3210
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// ↓↓↓↓
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// Input Port 3 → {4'b1111,
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// Input Port 2 → 4'b1111,
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// Input Port 1 → 4'b1111,
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// Input Port 0 → 4'b1111}
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//
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// Ports:
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//
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// s_axis_* : Slave port for router (flattened)
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// m_axis_* : Master port for router (flattened)
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// s_axis_mgmt_*: Management slave port
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// device_id : The ID of the device that has instantiated this module
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//
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module chdr_crossbar_nxn #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter [31:0] PORT_W = 64,
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parameter [7:0] NPORTS = 8,
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parameter [NPORTS*32-1:0] CHDR_WIDTHS = {NPORTS{PORT_W}},
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parameter EN_ROUTE_FIFO = 0,
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parameter EN_ROUTE_GATE = 0,
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parameter [7:0] DEFAULT_PORT = 0,
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parameter [NPORTS**2-1:0] ROUTES = {NPORTS*NPORTS{1'b1}},
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parameter BYTE_MTU = $clog2(8192),
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parameter ROUTE_TBL_SIZE = 6,
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parameter MUX_ALLOC = "ROUND-ROBIN",
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parameter OPTIMIZE = "AREA",
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parameter [7:0] NPORTS_MGMT = NPORTS,
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parameter EXT_RTCFG_PORT = 0
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) (
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input wire clk,
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input wire reset,
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// Device info
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input wire [15:0] device_id,
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// Inputs
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input wire [(PORT_W*NPORTS)-1:0] s_axis_tdata,
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input wire [NPORTS-1:0] s_axis_tlast,
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input wire [NPORTS-1:0] s_axis_tvalid,
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output wire [NPORTS-1:0] s_axis_tready,
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// Output
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output wire [(PORT_W*NPORTS)-1:0] m_axis_tdata,
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output wire [NPORTS-1:0] m_axis_tlast,
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output wire [NPORTS-1:0] m_axis_tvalid,
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input wire [NPORTS-1:0] m_axis_tready,
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// Router config management port
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input wire ext_rtcfg_stb,
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input wire [15:0] ext_rtcfg_addr,
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input wire [31:0] ext_rtcfg_data,
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output wire ext_rtcfg_ack
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);
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//---------------------------------------------------------------------------
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// RFNoC Includes
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//---------------------------------------------------------------------------
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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//---------------------------------------------------------------------------
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// Parameters
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//---------------------------------------------------------------------------
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localparam NPORTS_W = $clog2(NPORTS);
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localparam EPID_W = 16;
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localparam [17:0] EXT_INFO = {1'b0, EXT_RTCFG_PORT, NPORTS_MGMT, NPORTS};
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localparam [0:0] PKT_ST_HEAD = 1'b0;
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localparam [0:0] PKT_ST_BODY = 1'b1;
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//---------------------------------------------------------------------------
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// Functions
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//---------------------------------------------------------------------------
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// The compute_mux_alloc function is the switch allocation function for the
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// MUX. That is, it chooses which input port reserves the output MUX for
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// packet transfer.
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function [NPORTS_W-1:0] compute_mux_alloc(
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input [ NPORTS-1:0] pkt_waiting,
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input [NPORTS_W-1:0] last_alloc
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);
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reg signed [NPORTS_W:0] i;
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begin
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compute_mux_alloc = last_alloc;
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for (i = NPORTS-1; i >= 0; i=i-1) begin
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if (MUX_ALLOC == "PRIO") begin
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// Priority. Lower port index gets a higher priority.
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if (pkt_waiting[i]) begin
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compute_mux_alloc = i;
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end
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end else begin
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// Round-robin
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if (pkt_waiting[(last_alloc + i + 1) % NPORTS]) begin
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compute_mux_alloc = (last_alloc + i + 1) % NPORTS;
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end
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end
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end
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end
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endfunction
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// Return the CHDR width of the given port.
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function [31:0] CHDR_W(input integer n);
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CHDR_W = CHDR_WIDTHS[32*n +: 32];
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endfunction
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// Return the MTU size for the given port in terms of its CHDR width.
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function [31:0] WORD_MTU(input integer n);
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WORD_MTU = BYTE_MTU - $clog2(CHDR_W(n)/8);
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endfunction
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// Return bit indicating if the route between input port i and output port j
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// is enabled.
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function [0:0] ROUTE_ENABLED(input integer i, j);
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ROUTE_ENABLED = ROUTES[NPORTS*i + j];
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endfunction
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// Return bit indicating if the given input port has any routes connected to
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// it.
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function [0:0] INPUT_HAS_ROUTES(input integer i);
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INPUT_HAS_ROUTES = |ROUTES[NPORTS*i +: NPORTS];
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endfunction
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// Return bit indicating if the given output port has any routes connected to
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// it.
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function automatic [0:0] OUTPUT_HAS_ROUTES(input integer j);
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integer i;
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begin
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OUTPUT_HAS_ROUTES = 1'b0;
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for (i = 0; i < NPORTS; i = i+1) begin
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OUTPUT_HAS_ROUTES = OUTPUT_HAS_ROUTES | ROUTES[NPORTS*i + j];
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end
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end
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endfunction
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//---------------------------------------------------------------------------
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// CHDR Routing Table
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//---------------------------------------------------------------------------
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wire [NPORTS-1:0] rtcfg_req_wr;
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wire [(16*NPORTS)-1:0] rtcfg_req_addr;
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wire [(32*NPORTS)-1:0] rtcfg_req_data;
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wire [NPORTS-1:0] rtcfg_resp_ack;
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wire [(EPID_W*NPORTS)-1:0] find_tdata;
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wire [NPORTS-1:0] find_tvalid;
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wire [NPORTS-1:0] find_tready;
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wire [(NPORTS_W*NPORTS)-1:0] result_tdata;
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wire [NPORTS-1:0] result_tkeep;
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wire [NPORTS-1:0] result_tvalid;
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wire [NPORTS-1:0] result_tready;
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// Instantiate a single CAM-based routing table that will be shared between
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// all input ports. Configuration and lookup is performed using an AXI-Stream
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// interface. If multiple packets arrive simultaneously, only the headers of
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// those packets will be serialized in order to arbitrate this map. Selection
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// is done round-robin.
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chdr_xb_routing_table #(
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.SIZE(ROUTE_TBL_SIZE), .NPORTS(NPORTS),
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.EXT_INS_PORT_EN(EXT_RTCFG_PORT)
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) chdr_xb_routing_table_i (
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.clk (clk ),
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.reset (reset ),
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.port_req_wr (rtcfg_req_wr ),
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.port_req_addr (rtcfg_req_addr),
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.port_req_data (rtcfg_req_data),
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.port_resp_ack (rtcfg_resp_ack),
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.ext_req_wr (ext_rtcfg_stb ),
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.ext_req_addr (ext_rtcfg_addr),
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.ext_req_data (ext_rtcfg_data),
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.ext_resp_ack (ext_rtcfg_ack ),
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.axis_find_tdata (find_tdata ),
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.axis_find_tvalid (find_tvalid ),
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.axis_find_tready (find_tready ),
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.axis_result_tdata (result_tdata ),
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.axis_result_tkeep (result_tkeep ),
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.axis_result_tvalid(result_tvalid ),
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.axis_result_tready(result_tready )
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);
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wire [PORT_W-1:0] i_tdata [0:NPORTS-1];
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wire [9:0] i_tdest [0:NPORTS-1];
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wire [1:0] i_tid [0:NPORTS-1];
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wire i_tlast [0:NPORTS-1];
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wire i_tvalid [0:NPORTS-1];
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wire i_tready [0:NPORTS-1];
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wire [PORT_W-1:0] buf_tdata [0:NPORTS-1];
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wire [NPORTS_W-1:0] buf_tdest [0:NPORTS-1], buf_tdest_tmp[0:NPORTS-1];
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wire buf_tkeep [0:NPORTS-1];
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wire buf_tlast [0:NPORTS-1];
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wire buf_tvalid[0:NPORTS-1];
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wire buf_tready[0:NPORTS-1];
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wire [PORT_W-1:0] swi_tdata [0:NPORTS-1];
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wire [NPORTS_W-1:0] swi_tdest [0:NPORTS-1];
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wire swi_tlast [0:NPORTS-1];
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wire swi_tvalid[0:NPORTS-1];
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wire swi_tready[0:NPORTS-1];
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wire [(PORT_W*NPORTS)-1:0] swo_tdata [0:NPORTS-1], muxi_tdata [0:NPORTS-1];
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wire [NPORTS-1:0] swo_tlast [0:NPORTS-1], muxi_tlast [0:NPORTS-1];
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wire [NPORTS-1:0] swo_tvalid[0:NPORTS-1], muxi_tvalid[0:NPORTS-1];
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wire [NPORTS-1:0] swo_tready[0:NPORTS-1], muxi_tready[0:NPORTS-1];
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//---------------------------------------------------------------------------
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// Port Generation
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//---------------------------------------------------------------------------
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genvar n, i, j, port;
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generate
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for (n = 0; n < NPORTS; n = n + 1) begin: gen_in_ports
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// Only generate the input logic for this input port if it has routes
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if (INPUT_HAS_ROUTES(n)) begin : gen_in_port
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//-----------------------------------------------------------------------
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// Assertions
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//-----------------------------------------------------------------------
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// Make sure the width of this port does not exceed the given maximum
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// port width.
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if (CHDR_W(n) > PORT_W) begin : gen_chdr_w_too_large
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ERROR__CHDR_W_must_not_exceed_PORT_W_parameter();
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end
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// Make sure the port's CHDR width is a valid CHDR width (a power of 2
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// and at least 64 bits).
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if (2**$clog2(CHDR_W(n)) != CHDR_W(n) || CHDR_W(n) < 64) begin : gen_invalid_chdr_w
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ERROR__CHDR_W_is_not_a_valid_CHDR_width();
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end
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// Make sure the maximum port width is a valid CHDR width (a power of 2
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// and at least 64 bits).
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if (2**$clog2(PORT_W) != PORT_W || PORT_W < 64) begin : gen_invalid_port_w
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ERROR__PORT_W_is_not_a_valid_CHDR_width();
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end
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//-----------------------------------------------------------------------
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// Management Ports
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//-----------------------------------------------------------------------
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wire [47:0] node_info =
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chdr_mgmt_build_node_info(EXT_INFO, n, NODE_TYPE_XBAR, device_id);
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// For each input port, first check if we have a management packet
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// arriving. If it arrives, the top config commands are extracted, sent
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// to the routing table for configuration, and the rest of the packet is
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// forwarded down to the router. the router.
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if (n < NPORTS_MGMT) begin : gen_mgmt
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chdr_mgmt_pkt_handler #(
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.PROTOVER (PROTOVER ),
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.CHDR_W (CHDR_W(n)),
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.MGMT_ONLY (0 )
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) chdr_mgmt_pkt_handler_i (
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.clk (clk ),
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.rst (reset ),
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.node_info (node_info ),
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.s_axis_chdr_tdata (s_axis_tdata [(n*PORT_W)+:CHDR_W(n)]),
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.s_axis_chdr_tlast (s_axis_tlast [n] ),
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.s_axis_chdr_tvalid (s_axis_tvalid[n] ),
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.s_axis_chdr_tready (s_axis_tready[n] ),
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.s_axis_chdr_tuser (1'd0 ),
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.m_axis_chdr_tdata (i_tdata [n] ),
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.m_axis_chdr_tdest (i_tdest [n] ),
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.m_axis_chdr_tid (i_tid [n] ),
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.m_axis_chdr_tlast (i_tlast [n] ),
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.m_axis_chdr_tvalid (i_tvalid [n] ),
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.m_axis_chdr_tready (i_tready [n] ),
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.ctrlport_req_wr (rtcfg_req_wr [n] ),
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.ctrlport_req_rd (/* unused */ ),
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.ctrlport_req_addr (rtcfg_req_addr[(n*16)+:16] ),
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.ctrlport_req_data (rtcfg_req_data[(n*32)+:32] ),
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.ctrlport_resp_ack (rtcfg_resp_ack[n] ),
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.ctrlport_resp_data (32'h0 /* unused */ ),
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.op_stb (/* unused */ ),
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.op_dst_epid (/* unused */ ),
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.op_src_epid (/* unused */ ),
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.op_data (/* unused */ )
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);
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end else begin : gen_no_mgmt
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assign i_tdata [n] = s_axis_tdata [(n*PORT_W)+:CHDR_W(n)];
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assign i_tid [n] = CHDR_MGMT_ROUTE_EPID;
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assign i_tdest [n] = 10'd0; // Unused
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assign i_tlast [n] = s_axis_tlast [n];
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assign i_tvalid [n] = s_axis_tvalid[n];
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assign s_axis_tready[n] = i_tready [n];
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assign rtcfg_req_wr [n] = 1'b0;
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assign rtcfg_req_addr[(n*16)+:16] = 16'h0;
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assign rtcfg_req_data[(n*32)+:32] = 32'h0;
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end
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//-----------------------------------------------------------------------
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// Port Ingress Buffer
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//-----------------------------------------------------------------------
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// Ingress buffer module that does the following:
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// - Stores and gates an incoming packet
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// - Looks up destination in routing table and attaches a tdest for the packet
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chdr_xb_ingress_buff #(
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.WIDTH (CHDR_W(n) ),
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.MTU (WORD_MTU(n)),
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.DEST_W (NPORTS_W ),
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.NODE_ID(n )
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) chdr_xb_ingress_buff_i (
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.clk (clk ),
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.reset (reset ),
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.s_axis_chdr_tdata (i_tdata [n] ),
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.s_axis_chdr_tdest (i_tdest [n][NPORTS_W-1:0] ),
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.s_axis_chdr_tid (i_tid [n] ),
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.s_axis_chdr_tlast (i_tlast [n] ),
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.s_axis_chdr_tvalid (i_tvalid [n] ),
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.s_axis_chdr_tready (i_tready [n] ),
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.m_axis_chdr_tdata (buf_tdata [n] ),
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.m_axis_chdr_tdest (buf_tdest_tmp[n] ),
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.m_axis_chdr_tkeep (buf_tkeep [n] ),
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.m_axis_chdr_tlast (buf_tlast [n] ),
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.m_axis_chdr_tvalid (buf_tvalid [n] ),
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.m_axis_chdr_tready (buf_tready [n] ),
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.m_axis_find_tdata (find_tdata [(n*EPID_W)+:EPID_W] ),
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.m_axis_find_tvalid (find_tvalid [n] ),
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.m_axis_find_tready (find_tready [n] ),
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.s_axis_result_tdata (result_tdata [(n*NPORTS_W)+:NPORTS_W]),
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.s_axis_result_tkeep (result_tkeep [n] ),
|
|
.s_axis_result_tvalid(result_tvalid[n] ),
|
|
.s_axis_result_tready(result_tready[n] )
|
|
);
|
|
assign buf_tdest[n] = buf_tkeep[n] ? buf_tdest_tmp[n] : DEFAULT_PORT[NPORTS_W-1:0];
|
|
|
|
// Pipeline stage
|
|
axi_fifo #(
|
|
.WIDTH(CHDR_W(n)+1+NPORTS_W),
|
|
.SIZE (1 )
|
|
) axi_fifo_i (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.clear (1'b0 ),
|
|
.i_tdata ({buf_tlast[n], buf_tdest[n], buf_tdata[n][CHDR_W(n)-1:0]}),
|
|
.i_tvalid(buf_tvalid[n] ),
|
|
.i_tready(buf_tready[n] ),
|
|
.o_tdata ({swi_tlast[n], swi_tdest[n], swi_tdata[n][CHDR_W(n)-1:0]}),
|
|
.o_tvalid(swi_tvalid[n] ),
|
|
.o_tready(swi_tready[n] ),
|
|
.space (/* Unused */ ),
|
|
.occupied(/* Unused */ )
|
|
);
|
|
|
|
//-----------------------------------------------------------------------
|
|
// Ingress Switch (De-multiplexers)
|
|
//-----------------------------------------------------------------------
|
|
|
|
wire [CHDR_W(n)*NPORTS-1:0] swo_tdata_packed;
|
|
|
|
// Ingress de-mux. Use the tdest field to determine packet destination.
|
|
axis_switch #(
|
|
.DATA_W (CHDR_W(n)),
|
|
.DEST_W (1 ),
|
|
.IN_PORTS (1 ),
|
|
.OUT_PORTS(NPORTS ),
|
|
.PIPELINE (1 )
|
|
) axis_switch_demux (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.s_axis_tdata (swi_tdata[n][CHDR_W(n)-1:0]),
|
|
.s_axis_tdest ({1'b0, swi_tdest[n]} ),
|
|
.s_axis_tlast (swi_tlast [n] ),
|
|
.s_axis_tvalid(swi_tvalid[n] ),
|
|
.s_axis_tready(swi_tready[n] ),
|
|
.s_axis_alloc (1'b0 ),
|
|
.m_axis_tdata (swo_tdata_packed ),
|
|
.m_axis_tdest (/* Unused */ ),
|
|
.m_axis_tlast (swo_tlast [n] ),
|
|
.m_axis_tvalid(swo_tvalid[n] ),
|
|
.m_axis_tready(swo_tready[n] )
|
|
);
|
|
|
|
// Unpack the switch output to handle the case where this port's CHDR_W
|
|
// is narrower than PORT_W.
|
|
for (port = 0; port < NPORTS; port = port+1) begin : gen_switch_output
|
|
assign swo_tdata[n][PORT_W*port +: CHDR_W(n)] =
|
|
swo_tdata_packed[CHDR_W(n)*port +: CHDR_W(n)];
|
|
end
|
|
end // gen_in_port
|
|
end // gen_in_ports
|
|
|
|
//-------------------------------------------------------------------------
|
|
// Crossbar Routing
|
|
//-------------------------------------------------------------------------
|
|
|
|
// Generate the routing for a full NxN crossbar where i is the input port
|
|
// number and j is the output port number. Some paths are resized,
|
|
// depending on CHDR_WIDTHS, or excluded, depending on ROUTES.
|
|
for (i = 0; i < NPORTS; i = i + 1) begin : gen_for_i
|
|
for (j = 0; j < NPORTS; j = j + 1) begin : gen_for_j
|
|
if (ROUTE_ENABLED(i,j)) begin : gen_enabled_route
|
|
wire [CHDR_W(i)-1:0] rs_i_tdata;
|
|
wire rs_i_tlast;
|
|
wire rs_i_tvalid;
|
|
wire rs_i_tready;
|
|
|
|
wire [CHDR_W(j)-1:0] rs_o_tdata;
|
|
wire rs_o_tlast;
|
|
wire rs_o_tvalid;
|
|
wire rs_o_tready;
|
|
|
|
// Connect output j of ingress port i to input i of egress port j.
|
|
// Resize the bus if the ports have different widths, otherwise
|
|
// directly connect them.
|
|
if (CHDR_W(i) != CHDR_W(j)) begin : gen_port_resize
|
|
if (CHDR_W(i) > CHDR_W(j) && EN_ROUTE_FIFO) begin : gen_input_fifo
|
|
// If we're downsizing, we need a wide FIFO on the input to the
|
|
// resize block to buffer the fast incoming packet.
|
|
axi_fifo #(
|
|
.WIDTH(CHDR_W(i)+1),
|
|
.SIZE (WORD_MTU(i))
|
|
) axi_fifo_i (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.clear (1'b0 ),
|
|
.i_tdata ({swo_tlast[i][j], swo_tdata[i][j*PORT_W+:CHDR_W(i)]}),
|
|
.i_tvalid(swo_tvalid[i][j] ),
|
|
.i_tready(swo_tready[i][j] ),
|
|
.o_tdata ({rs_i_tlast, rs_i_tdata} ),
|
|
.o_tvalid(rs_i_tvalid ),
|
|
.o_tready(rs_i_tready ),
|
|
.space ( ),
|
|
.occupied( )
|
|
);
|
|
end else begin : gen_no_input_fifo
|
|
assign rs_i_tdata = swo_tdata[i][j*PORT_W+:CHDR_W(i)];
|
|
assign rs_i_tlast = swo_tlast[i][j];
|
|
assign rs_i_tvalid = swo_tvalid[i][j];
|
|
assign swo_tready[i][j] = rs_i_tready;
|
|
end
|
|
|
|
chdr_resize #(
|
|
.I_CHDR_W(CHDR_W(i)),
|
|
.O_CHDR_W(CHDR_W(j)),
|
|
.I_DATA_W(CHDR_W(i)),
|
|
.O_DATA_W(CHDR_W(j)),
|
|
.USER_W (1 ),
|
|
.PIPELINE("OUT" )
|
|
) chdr_resize_i (
|
|
.clk (clk ),
|
|
.rst (reset ),
|
|
.i_chdr_tdata (rs_i_tdata ),
|
|
.i_chdr_tuser (1'b0 ),
|
|
.i_chdr_tlast (rs_i_tlast ),
|
|
.i_chdr_tvalid(rs_i_tvalid),
|
|
.i_chdr_tready(rs_i_tready),
|
|
.o_chdr_tdata (rs_o_tdata ),
|
|
.o_chdr_tuser ( ),
|
|
.o_chdr_tlast (rs_o_tlast ),
|
|
.o_chdr_tvalid(rs_o_tvalid),
|
|
.o_chdr_tready(rs_o_tready)
|
|
);
|
|
|
|
if (CHDR_W(i) < CHDR_W(j) && EN_ROUTE_GATE) begin : gen_output_pkt_gate
|
|
// If we are up-sizing, then there will be idle cycles on the
|
|
// wider output bus that will waste time on the output mux. To
|
|
// maximize throughput on the output port, we gate packets here
|
|
// so that we can output a continuous stream of data without idle
|
|
// cycles.
|
|
axi_packet_gate #(
|
|
.WIDTH(CHDR_W(j) ),
|
|
.SIZE (WORD_MTU(j))
|
|
) axi_packet_gate_i (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.clear (1'b0 ),
|
|
.i_tdata (rs_o_tdata ),
|
|
.i_tlast (rs_o_tlast ),
|
|
.i_terror(1'b0 ),
|
|
.i_tvalid(rs_o_tvalid ),
|
|
.i_tready(rs_o_tready ),
|
|
.o_tdata (muxi_tdata[j][i*PORT_W+:CHDR_W(j)]),
|
|
.o_tlast (muxi_tlast[j][i] ),
|
|
.o_tvalid(muxi_tvalid[j][i] ),
|
|
.o_tready(muxi_tready[j][i] )
|
|
);
|
|
end else begin : gen_no_output_pkt_gate
|
|
assign muxi_tdata[j][i*PORT_W+:CHDR_W(j)] = rs_o_tdata;
|
|
assign muxi_tlast[j][i] = rs_o_tlast;
|
|
assign muxi_tvalid[j][i] = rs_o_tvalid;
|
|
assign rs_o_tready = muxi_tready[j][i];
|
|
end
|
|
|
|
end else begin : gen_port_same_size
|
|
assign muxi_tdata[j][i*PORT_W+:CHDR_W(j)] = swo_tdata [i][j*PORT_W+:CHDR_W(i)];
|
|
assign muxi_tlast[j][i] = swo_tlast [i][j];
|
|
assign muxi_tvalid[j][i] = swo_tvalid [i][j];
|
|
assign swo_tready[i][j] = muxi_tready[j][i];
|
|
end
|
|
end else begin : gen_disabled_route
|
|
// Tie off these unused paths so they can be optimized out.
|
|
assign muxi_tdata[j][i*PORT_W+:PORT_W] = { PORT_W {1'b0} };
|
|
assign muxi_tlast[j][i] = 1'b0;
|
|
assign muxi_tvalid[j][i] = 1'b0;
|
|
assign swo_tready[i][j] = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
//-------------------------------------------------------------------------
|
|
// Egress Switch (Multiplexers)
|
|
//-------------------------------------------------------------------------
|
|
|
|
for (n = 0; n < NPORTS; n = n + 1) begin: gen_out_ports
|
|
// Only generate egress logic for this output port if it has routes
|
|
if (OUTPUT_HAS_ROUTES(n)) begin : gen_out_port
|
|
wire [CHDR_W(n)*NPORTS-1:0] muxi_tdata_repacked;
|
|
|
|
// Repack the mux input to handle the case where this port's CHDR_W is
|
|
// narrower than PORT_W.
|
|
for (port = 0; port < NPORTS; port = port+1) begin : gen_mux_input
|
|
assign muxi_tdata_repacked[CHDR_W(n)*port +: CHDR_W(n)] =
|
|
muxi_tdata[n][PORT_W*port +: CHDR_W(n)];
|
|
end
|
|
|
|
if (OPTIMIZE == "PERFORMANCE") begin : gen_performance
|
|
// Use the axis_switch module when optimizing for performance
|
|
// This logic has some extra levels of logic to ensure
|
|
// that the switch allocation happens in 0 clock cycles which
|
|
// means that Fmax for this implementation will be lower.
|
|
|
|
wire mux_ready = |muxi_tready[n]; // Max 1 bit should be high
|
|
wire mux_valid = |muxi_tvalid[n];
|
|
wire mux_last = |(muxi_tvalid[n] & muxi_tlast[n]);
|
|
|
|
// Track the input packet state
|
|
reg [0:0] pkt_state = PKT_ST_HEAD;
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
pkt_state <= PKT_ST_HEAD;
|
|
end else if (mux_valid & mux_ready) begin
|
|
pkt_state <= mux_last ? PKT_ST_HEAD : PKT_ST_BODY;
|
|
end
|
|
end
|
|
|
|
// The switch requires the allocation to stay valid until the
|
|
// end of the packet. We also might need to keep the previous
|
|
// packet's allocation to compute the current one
|
|
reg [NPORTS_W-1:0] prev_sw_alloc = {NPORTS_W{1'b0}};
|
|
reg [NPORTS_W-1:0] pkt_sw_alloc = {NPORTS_W{1'b0}};
|
|
wire [NPORTS_W-1:0] muxi_sw_alloc = (mux_valid && pkt_state == PKT_ST_HEAD) ?
|
|
compute_mux_alloc(muxi_tvalid[n], prev_sw_alloc) : pkt_sw_alloc;
|
|
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
prev_sw_alloc <= {NPORTS_W{1'b0}};
|
|
pkt_sw_alloc <= {NPORTS_W{1'b0}};
|
|
end else if (mux_valid & mux_ready) begin
|
|
if (pkt_state == PKT_ST_HEAD)
|
|
pkt_sw_alloc <= muxi_sw_alloc;
|
|
if (mux_last)
|
|
prev_sw_alloc <= muxi_sw_alloc;
|
|
end
|
|
end
|
|
|
|
axis_switch #(
|
|
.DATA_W (CHDR_W(n)),
|
|
.DEST_W (1 ),
|
|
.IN_PORTS (NPORTS ),
|
|
.OUT_PORTS (1 ),
|
|
.PIPELINE (0 )
|
|
) axis_switch_mux (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.s_axis_tdata (muxi_tdata_repacked ),
|
|
.s_axis_tdest ({NPORTS{1'b0}} /* Unused */ ),
|
|
.s_axis_tlast (muxi_tlast [n] ),
|
|
.s_axis_tvalid (muxi_tvalid[n] ),
|
|
.s_axis_tready (muxi_tready[n] ),
|
|
.s_axis_alloc (muxi_sw_alloc ),
|
|
.m_axis_tdata (m_axis_tdata [(n*PORT_W)+:CHDR_W(n)]),
|
|
.m_axis_tdest (/* Unused */ ),
|
|
.m_axis_tlast (m_axis_tlast [n] ),
|
|
.m_axis_tvalid (m_axis_tvalid[n] ),
|
|
.m_axis_tready (m_axis_tready[n] )
|
|
);
|
|
end else begin : gen_not_performance
|
|
// axi_mux has an additional bubble cycle but the logic
|
|
// to allocate an input port has fewer levels and takes
|
|
// up fewer resources.
|
|
axi_mux #(
|
|
.PRIO (MUX_ALLOC == "PRIO" ),
|
|
.WIDTH (CHDR_W(n) ),
|
|
.SIZE (NPORTS ),
|
|
.PRE_FIFO_SIZE (OPTIMIZE == "TIMING" ? 1 : 0),
|
|
.POST_FIFO_SIZE(1 )
|
|
) axi_mux_i (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.clear (1'b0 ),
|
|
.i_tdata (muxi_tdata_repacked ),
|
|
.i_tlast (muxi_tlast [n] ),
|
|
.i_tvalid(muxi_tvalid [n] ),
|
|
.i_tready(muxi_tready [n] ),
|
|
.o_tdata (m_axis_tdata [(n*PORT_W)+:CHDR_W(n)]),
|
|
.o_tlast (m_axis_tlast [n] ),
|
|
.o_tvalid(m_axis_tvalid[n] ),
|
|
.o_tready(m_axis_tready[n] )
|
|
);
|
|
end
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
|
|
endmodule
|