7e59e9516d
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
21 lines
680 B
Tcl
21 lines
680 B
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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#
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# Timing constants for the MB CPLD <-> DB CPLD SPI interface
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#
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# Delays are rounded to integer values which leave a slack of >1ns on each setup
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# and hold path without requirement for adding hold delays (as reported
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# by Quartus fitter report).
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# The signal might change before the SCLK edge as the internal
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# registers are driven by PLL reference clock rather than the SPI clock used
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# for the port timing constaints.
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set db_cpld_spi_max_out 14.000
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set db_cpld_spi_min_out 2.000
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set db_cpld_spi_max_in 2.000
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set db_cpld_spi_min_in -2.000
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