Wade Fife bdc67122b8 fpga: tools: Detect assertions in ModelSim simulation ...

This change allows assertion errors/failures in ModelSim to be
detected and causes ModelSim to return a non-zero value when such
an assertion error occurs. This allows the return value of ModelSim
to be used to determine whether or not the testbench passed.


Original-commit: 574146ec8909da367c3441189c2877a287892f7e

2021-06-17 08:16:59 -05:00

..

check_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

git-hash.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ise_jtag_program.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_modelsim.sh

fpga: tools: Detect assertions in ModelSim simulation

2021-06-17 08:16:59 -05:00

launch_vivado.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

launch_vivado.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_vlint.sh

fpga: tools: Put SIM_SRCS at end of compile order

2021-06-17 08:16:59 -05:00

setupenv_base.sh

fpga: tools: Add modelsim.ini to ModelSim calls

2021-06-17 08:16:59 -05:00

shared-ip-loc-manage.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_check_syntax.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_gen_ip_makefile.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_gen_part_id.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_generate_bd.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_hls_ip.tcl

fpga: tools: Fix HLS IP build with Cygwin

2020-05-12 13:47:20 -05:00

viv_generate_ip.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_patch_ip.tcl

fpga: tools: Add ability to patch IP during generation

2021-06-03 10:22:04 -05:00

viv_hardware_utils.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_ip_utils.tcl

fpga: tools: Ignore BD layout info for TCL-based BD

2020-03-12 10:33:24 -05:00

viv_ip_xci_editor.py

fpga: tools: Add support for RFSoC

2021-06-03 10:22:04 -05:00

viv_sim_project.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

viv_strategies.tcl

fpga: tools: Add ability to run commands before route

2021-06-03 10:22:04 -05:00

viv_synth.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_utils.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

xil_bitfile_parser.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00