21 lines
716 B
VHDL
21 lines
716 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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package zpu_config is
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-- generate trace output or not.
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constant Generate_Trace : boolean := false;
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constant wordPower : integer := 5;
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-- during simulation, set this to '0' to get matching trace.txt
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constant DontCareValue : std_logic := '0';
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-- Clock frequency in MHz.
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constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
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-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
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constant maxAddrBitIncIO : integer := 15;
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-- start byte address of stack.
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-- point to top of RAM - 2*words
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constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"7ff8";
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end zpu_config;
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