349 lines
20 KiB
Verilog
349 lines
20 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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`define GET_DMA_BUS(parallel_bus, chan_idx) parallel_bus[(DMA_STREAM_WIDTH*(chan_idx+1))-1:(DMA_STREAM_WIDTH*chan_idx)]
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`define GET_FSIZE_BUS(parallel_bus, chan_idx) parallel_bus[(DMA_FRAME_SIZE_WIDTH*(chan_idx+1))-1:(DMA_FRAME_SIZE_WIDTH*chan_idx)]
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`define GET_SWAP_BUS(parallel_bus, chan_idx) parallel_bus[(3*(chan_idx+1))-1:(3*chan_idx)]
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module x300_pcie_int #(
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parameter DMA_STREAM_WIDTH = 64,
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parameter NUM_TX_STREAMS = 6,
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parameter NUM_RX_STREAMS = 6,
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parameter REGPORT_ADDR_WIDTH = 20,
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parameter REGPORT_DATA_WIDTH = 32,
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parameter IOP2_MSG_WIDTH = 64
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) (
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//---------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------
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input ioport2_clk,
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input bus_clk,
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input bus_rst,
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//---------------------------------------------------------
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// DMA streams to/from Chinch Interface to IoPort2 (Domain: ioport2_clk)
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//---------------------------------------------------------
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input [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2,
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input [NUM_TX_STREAMS-1:0] dmatx_tvalid_iop2,
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output [NUM_TX_STREAMS-1:0] dmatx_tready_iop2,
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output [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2,
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output [NUM_RX_STREAMS-1:0] dmarx_tvalid_iop2,
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input [NUM_RX_STREAMS-1:0] dmarx_tready_iop2,
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//---------------------------------------------------------
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// DMA stream to/from crossbar (Domain: bus_clk)
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//---------------------------------------------------------
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output [DMA_STREAM_WIDTH-1:0] dmatx_tdata,
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output dmatx_tvalid,
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output dmatx_tlast,
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input dmatx_tready,
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input [DMA_STREAM_WIDTH-1:0] dmarx_tdata,
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input dmarx_tvalid,
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input dmarx_tlast,
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output dmarx_tready,
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//---------------------------------------------------------
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// PCIe User register port (Domain: ioport2_clk)
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//---------------------------------------------------------
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input pcie_usr_reg_wr,
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input pcie_usr_reg_rd,
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input [REGPORT_ADDR_WIDTH-1:0] pcie_usr_reg_addr,
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input [REGPORT_DATA_WIDTH-1:0] pcie_usr_reg_data_in,
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input [1:0] pcie_usr_reg_len,
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output [REGPORT_DATA_WIDTH-1:0] pcie_usr_reg_data_out,
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output pcie_usr_reg_rc,
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output pcie_usr_reg_rdy,
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//---------------------------------------------------------
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// PCIe Chinch register port (Domain: ioport2_clk)
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//---------------------------------------------------------
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output chinch_reg_wr,
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output chinch_reg_rd,
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output [REGPORT_ADDR_WIDTH-1:0] chinch_reg_addr,
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output [REGPORT_DATA_WIDTH-1:0] chinch_reg_data_out,
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output [1:0] chinch_reg_len,
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input [REGPORT_DATA_WIDTH-1:0] chinch_reg_data_in,
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input chinch_reg_rc,
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input chinch_reg_rdy,
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//---------------------------------------------------------
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// Message FIFOs to/from the core logic (Domain: bus_clk)
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//---------------------------------------------------------
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input [IOP2_MSG_WIDTH-1:0] rego_tdata,
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input rego_tvalid,
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input rego_tlast,
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output rego_tready,
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output [IOP2_MSG_WIDTH-1:0] regi_tdata,
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output regi_tvalid,
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output regi_tlast,
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input regi_tready,
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//---------------------------------------------------------
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// Misc
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//---------------------------------------------------------
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input [31:0] misc_status,
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output [127:0] debug
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);
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localparam REG_CLK_XING_FIFO_SIZE = 5; //Will synthesize fifo_short_2clk
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localparam DMA_CLK_XING_FIFO_SIZE = 5; //Will synthesize fifo_short_2clk
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localparam DMA_PKT_GATE_FIFO_SIZE = 11; //Room for 2 8k packets
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localparam DMA_FRAME_SIZE_WIDTH = 16;
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localparam DMA_RX_DEST_WIDTH = 3;
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//*******************************************************************************
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// Message FIFO translator + clock crossing
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//
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wire msgo_tvalid, msgi_tvalid, msgo_tready, msgi_tready;
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wire [63:0] msgo_tdata, msgi_tdata;
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wire pcie_out_valid, pcie_in_valid;
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wire [63:0] pcie_out_msg, pcie_in_msg;
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//Link chinch register port and user register port to AXI message FIFOs
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wire iop2_rd_response, iop2_wr_request, iop2_rd_request;
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wire [31:0] iop2_data;
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wire chinch_reg_is_half_word;
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ioport2_msg_decode pcie_out_msg_decoder (
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.message(pcie_out_msg),
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.rd_response(iop2_rd_response), .wr_request(iop2_wr_request), .rd_request(iop2_rd_request), .half_word(chinch_reg_is_half_word),
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.address(chinch_reg_addr), .data(iop2_data));
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assign chinch_reg_len = chinch_reg_is_half_word ? 2'b01 : 2'b10;
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assign pcie_usr_reg_rc = iop2_rd_response & pcie_out_valid;
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assign chinch_reg_wr = iop2_wr_request & pcie_out_valid;
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assign chinch_reg_rd = iop2_rd_request & pcie_out_valid;
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assign chinch_reg_data_out = iop2_data;
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assign pcie_usr_reg_data_out = iop2_data;
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ioport2_msg_encode pcie_in_msg_encoder (
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.rd_response(chinch_reg_rc), .wr_request(pcie_usr_reg_wr), .rd_request(pcie_usr_reg_rd), .half_word(pcie_usr_reg_len == 2'b01),
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.address(pcie_usr_reg_addr), .data(chinch_reg_rc ? chinch_reg_data_in : pcie_usr_reg_data_in),
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.message(pcie_in_msg));
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assign pcie_in_valid = chinch_reg_rc | pcie_usr_reg_wr | pcie_usr_reg_rd;
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//Cross from the Ioport2 clock domain to the bus clock domain
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axi_fifo_2clk #(.WIDTH(64), .SIZE(REG_CLK_XING_FIFO_SIZE)) pcie_out_msg_fifo (
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.reset(bus_rst),
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.i_aclk(bus_clk), .i_tdata(msgo_tdata), .i_tvalid(msgo_tvalid), .i_tready(msgo_tready),
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.o_aclk(ioport2_clk), .o_tdata(pcie_out_msg), .o_tvalid(pcie_out_valid), .o_tready(chinch_reg_rdy | pcie_usr_reg_rc));
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axi_fifo_2clk #(.WIDTH(64), .SIZE(REG_CLK_XING_FIFO_SIZE)) pcie_in_msg_fifo (
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.reset(bus_rst),
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.i_aclk(ioport2_clk), .i_tdata(pcie_in_msg), .i_tvalid(pcie_in_valid), .i_tready(pcie_usr_reg_rdy),
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.o_aclk(bus_clk), .o_tdata(msgi_tdata), .o_tvalid(msgi_tvalid), .o_tready(msgi_tready));
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//
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//*******************************************************************************
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wire [NUM_TX_STREAMS-1:0] dmatx_clear, dmatx_samp_stb, dmatx_pkt_stb, dmatx_error;
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wire [(NUM_TX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmatx_frame_size;
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wire [(NUM_TX_STREAMS*3)-1:0] dmatx_swap;
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wire [NUM_RX_STREAMS-1:0] dmarx_clear, dmarx_samp_stb, dmarx_pkt_stb, dmarx_error;
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wire [(NUM_RX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmarx_frame_size;
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wire [(NUM_TX_STREAMS*3)-1:0] dmarx_swap;
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wire [DMA_STREAM_WIDTH-1:0] dmarx_header;
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wire [DMA_RX_DEST_WIDTH-1:0] dmarx_pkt_dest;
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//*******************************************************************************
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// PCIe message/register endpoints
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//
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wire [63:0] basic_regi_tdata, dmatx_regi_tdata, dmarx_regi_tdata;
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wire basic_regi_tvalid, dmatx_regi_tvalid, dmarx_regi_tvalid;
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wire basic_regi_tready, dmatx_regi_tready, dmarx_regi_tready;
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wire [63:0] basic_rego_tdata, dmatx_rego_tdata, dmarx_rego_tdata;
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wire basic_rego_tvalid, dmatx_rego_tvalid, dmarx_rego_tvalid;
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wire basic_rego_tready, dmatx_rego_tready, dmarx_rego_tready;
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pcie_iop2_msg_arbiter #(
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//(DO NOT USE) //0x00000 - 0x3FFFC: Reserved LVFPGA Core Space
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.E0_ADDR(20'h40000), .E0_MASK(20'hFFE00), //0x40000 - 0x401FC: Basic PCIe registers
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.E1_ADDR(20'h40200), .E1_MASK(20'hFFE00), //0x40200 - 0x403FC: TX DMA Config/Readback registers
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.E2_ADDR(20'h40400), .E2_MASK(20'hFFE00), //0x40400 - 0x405FC: RX DMA Config/Readback registers
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.E3_ADDR(20'h60000), .E3_MASK(20'hE0000) //0x60000 - 0x7FFFC: Client address space
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) iop2_msg_arbiter (
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.clk(bus_clk), .reset(bus_rst),
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//Master
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.regi_tdata(msgi_tdata), .regi_tvalid(msgi_tvalid), .regi_tready(msgi_tready),
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.rego_tdata(msgo_tdata), .rego_tvalid(msgo_tvalid), .rego_tready(msgo_tready),
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//Endpoint 0
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.e0_regi_tdata(basic_regi_tdata), .e0_regi_tvalid(basic_regi_tvalid), .e0_regi_tready(basic_regi_tready),
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.e0_rego_tdata(basic_rego_tdata), .e0_rego_tvalid(basic_rego_tvalid), .e0_rego_tready(basic_rego_tready),
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//Endpoint 1
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.e1_regi_tdata(dmatx_regi_tdata), .e1_regi_tvalid(dmatx_regi_tvalid), .e1_regi_tready(dmatx_regi_tready),
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.e1_rego_tdata(dmatx_rego_tdata), .e1_rego_tvalid(dmatx_rego_tvalid), .e1_rego_tready(dmatx_rego_tready),
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//Endpoint 2
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.e2_regi_tdata(dmarx_regi_tdata), .e2_regi_tvalid(dmarx_regi_tvalid), .e2_regi_tready(dmarx_regi_tready),
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.e2_rego_tdata(dmarx_rego_tdata), .e2_rego_tvalid(dmarx_rego_tvalid), .e2_rego_tready(dmarx_rego_tready),
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//Endpoint 3
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.e3_regi_tdata(regi_tdata), .e3_regi_tvalid(regi_tvalid), .e3_regi_tready(regi_tready),
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.e3_rego_tdata(rego_tdata), .e3_rego_tvalid(rego_tvalid), .e3_rego_tready(rego_tready)
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);
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assign regi_tlast = regi_tvalid;
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pcie_basic_regs basic_regs (
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.clk(bus_clk), .reset(bus_rst),
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.regi_tdata(basic_regi_tdata), .regi_tvalid(basic_regi_tvalid), .regi_tready(basic_regi_tready),
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.rego_tdata(basic_rego_tdata), .rego_tvalid(basic_rego_tvalid), .rego_tready(basic_rego_tready),
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.misc_status(misc_status)
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);
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pcie_dma_ctrl #(
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.NUM_STREAMS(NUM_TX_STREAMS), .FRAME_SIZE_W(DMA_FRAME_SIZE_WIDTH),
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.REG_BASE_ADDR(20'h40200), .ENABLE_ROUTER(0)
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) tx_dma_ctrl_regs (
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.clk(bus_clk), .reset(bus_rst),
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.regi_tdata(dmatx_regi_tdata), .regi_tvalid(dmatx_regi_tvalid), .regi_tready(dmatx_regi_tready),
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.rego_tdata(dmatx_rego_tdata), .rego_tvalid(dmatx_rego_tvalid), .rego_tready(dmatx_rego_tready),
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.set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size), .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb),
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.swap_lanes(dmatx_swap), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
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);
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pcie_dma_ctrl #(
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.NUM_STREAMS(NUM_RX_STREAMS), .FRAME_SIZE_W(DMA_FRAME_SIZE_WIDTH),
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.REG_BASE_ADDR(20'h40400), .ENABLE_ROUTER(1), .ROUTER_SID_W(8), .ROUTER_DST_W(DMA_RX_DEST_WIDTH)
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) rx_dma_ctrl_regs (
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.clk(bus_clk), .reset(bus_rst),
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.regi_tdata(dmarx_regi_tdata), .regi_tvalid(dmarx_regi_tvalid), .regi_tready(dmarx_regi_tready),
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.rego_tdata(dmarx_rego_tdata), .rego_tvalid(dmarx_rego_tvalid), .rego_tready(dmarx_rego_tready),
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.set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size), .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb),
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.swap_lanes(dmarx_swap), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
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);
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//
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//*******************************************************************************
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//*******************************************************************************
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// TX DMA Datapath
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//
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wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_bclk, dmatx_tdata_trun, dmatx_tdata_gt, dmatx_tdata_swap;
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wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_bclk, dmatx_tvalid_trun, dmatx_tvalid_gt;
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wire [NUM_TX_STREAMS-1:0] dmatx_tready_bclk, dmatx_tready_trun, dmatx_tready_gt;
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wire [NUM_TX_STREAMS-1:0] dmatx_tlast_trun, dmatx_tlast_gt;
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wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata_mux;
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wire dmatx_tvalid_mux, dmatx_tlast_mux, dmatx_tready_mux;
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genvar i;
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generate
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for (i=0; i<NUM_TX_STREAMS; i=i+1) begin: tx_dma_stuff_generator
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axi_fifo_2clk #(.WIDTH(DMA_STREAM_WIDTH), .SIZE(DMA_CLK_XING_FIFO_SIZE)) tx_dma_clock_crossing_fifo (
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.reset(bus_rst),
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.i_aclk(ioport2_clk), .i_tdata(`GET_DMA_BUS(dmatx_tdata_iop2,i)), .i_tvalid(dmatx_tvalid_iop2[i]), .i_tready(dmatx_tready_iop2[i]),
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.o_aclk(bus_clk), .o_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tvalid(dmatx_tvalid_bclk[i]), .o_tready(dmatx_tready_bclk[i])
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);
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data_swapper_64 tx_data_swapper (
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.swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
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);
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cvita_dechunker tx_dma_dechunker (
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.clk(bus_clk), .reset(bus_rst), .clear(dmatx_clear[i]), .frame_size(`GET_FSIZE_BUS(dmatx_frame_size, i)),
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.i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
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.o_tdata(`GET_DMA_BUS(dmatx_tdata_trun,i)), .o_tlast(dmatx_tlast_trun[i]), .o_tvalid(dmatx_tvalid_trun[i]), .o_tready(dmatx_tready_trun[i]),
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.error(dmatx_error[i])
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);
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assign dmatx_samp_stb[i] = dmatx_tvalid_trun[i] & dmatx_tready_trun[i];
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assign dmatx_pkt_stb[i] = dmatx_samp_stb[i] & dmatx_tlast_trun[i];
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axi_packet_gate #(.WIDTH(DMA_STREAM_WIDTH), .SIZE(DMA_PKT_GATE_FIFO_SIZE)) vita_chdr_gate (
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.clk(bus_clk), .reset(bus_rst), .clear(dmatx_clear[i]),
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.i_tdata(`GET_DMA_BUS(dmatx_tdata_trun,i)), .i_tlast(dmatx_tlast_trun[i]), .i_tvalid(dmatx_tvalid_trun[i]), .i_tready(dmatx_tready_trun[i]),
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.i_terror(dmatx_error[i]),
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.o_tdata(`GET_DMA_BUS(dmatx_tdata_gt,i)), .o_tlast(dmatx_tlast_gt[i]), .o_tvalid(dmatx_tvalid_gt[i]), .o_tready(dmatx_tready_gt[i])
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);
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end
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endgenerate
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axi_mux8 #(.PRIO(0), .WIDTH(DMA_STREAM_WIDTH)) output_dma_mux (
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.clk(bus_clk), .reset(bus_rst), .clear(|(dmatx_clear)),
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.i0_tdata(`GET_DMA_BUS(dmatx_tdata_gt,0)), .i0_tlast(dmatx_tlast_gt[0]), .i0_tvalid(dmatx_tvalid_gt[0]), .i0_tready(dmatx_tready_gt[0]),
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.i1_tdata(`GET_DMA_BUS(dmatx_tdata_gt,1)), .i1_tlast(dmatx_tlast_gt[1]), .i1_tvalid(dmatx_tvalid_gt[1]), .i1_tready(dmatx_tready_gt[1]),
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.i2_tdata(`GET_DMA_BUS(dmatx_tdata_gt,2)), .i2_tlast(dmatx_tlast_gt[2]), .i2_tvalid(dmatx_tvalid_gt[2]), .i2_tready(dmatx_tready_gt[2]),
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.i3_tdata(`GET_DMA_BUS(dmatx_tdata_gt,3)), .i3_tlast(dmatx_tlast_gt[3]), .i3_tvalid(dmatx_tvalid_gt[3]), .i3_tready(dmatx_tready_gt[3]),
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.i4_tdata(`GET_DMA_BUS(dmatx_tdata_gt,4)), .i4_tlast(dmatx_tlast_gt[4]), .i4_tvalid(dmatx_tvalid_gt[4]), .i4_tready(dmatx_tready_gt[4]),
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.i5_tdata(`GET_DMA_BUS(dmatx_tdata_gt,5)), .i5_tlast(dmatx_tlast_gt[5]), .i5_tvalid(dmatx_tvalid_gt[5]), .i5_tready(dmatx_tready_gt[5]),
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.i6_tdata(0), .i6_tlast(1'b0), .i6_tvalid(1'b0), .i6_tready(),
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.i7_tdata(0), .i7_tlast(1'b0), .i7_tvalid(1'b0), .i7_tready(),
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.o_tdata(dmatx_tdata_mux), .o_tlast(dmatx_tlast_mux), .o_tvalid(dmatx_tvalid_mux), .o_tready(dmatx_tready_mux)
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);
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axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1)) tx_pipeline_srl (
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.clk(bus_clk), .reset(bus_rst), .clear(|(dmatx_clear)),
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.i_tdata({dmatx_tlast_mux, dmatx_tdata_mux}), .i_tvalid(dmatx_tvalid_mux), .i_tready(dmatx_tready_mux),
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.o_tdata({dmatx_tlast, dmatx_tdata}), .o_tvalid(dmatx_tvalid), .o_tready(dmatx_tready),
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.space(), .occupied());
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//
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//*******************************************************************************
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//*******************************************************************************
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// RX DMA Datapath
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//
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wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_bclk, dmarx_tdata_pad, dmarx_tdata_swap;
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wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_bclk, dmarx_tvalid_pad;
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wire [NUM_RX_STREAMS-1:0] dmarx_tready_bclk, dmarx_tready_pad;
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wire [NUM_RX_STREAMS-1:0] dmarx_tlast_bclk, dmarx_tlast_pad;
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wire [DMA_STREAM_WIDTH-1:0] dmarx_tdata_mux;
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wire dmarx_tvalid_mux, dmarx_tlast_mux, dmarx_tready_mux;
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axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1)) rx_pipeline_srl (
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.clk(bus_clk), .reset(bus_rst), .clear(|(dmarx_clear)),
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.i_tdata({dmarx_tlast, dmarx_tdata}), .i_tvalid(dmarx_tvalid), .i_tready(dmarx_tready),
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.o_tdata({dmarx_tlast_mux, dmarx_tdata_mux}), .o_tvalid(dmarx_tvalid_mux), .o_tready(dmarx_tready_mux),
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.space(), .occupied());
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axi_demux8 #(.ACTIVE_CHAN(8'b00111111), .WIDTH(DMA_STREAM_WIDTH)) input_dma_demux (
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.clk(bus_clk), .reset(bus_rst), .clear(|(dmarx_clear)),
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.header(dmarx_header), .dest(dmarx_pkt_dest),
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.i_tdata(dmarx_tdata_mux), .i_tlast(dmarx_tlast_mux), .i_tvalid(dmarx_tvalid_mux), .i_tready(dmarx_tready_mux),
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.o0_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,0)), .o0_tlast(dmarx_tlast_bclk[0]), .o0_tvalid(dmarx_tvalid_bclk[0]), .o0_tready(dmarx_tready_bclk[0]),
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.o1_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,1)), .o1_tlast(dmarx_tlast_bclk[1]), .o1_tvalid(dmarx_tvalid_bclk[1]), .o1_tready(dmarx_tready_bclk[1]),
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.o2_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,2)), .o2_tlast(dmarx_tlast_bclk[2]), .o2_tvalid(dmarx_tvalid_bclk[2]), .o2_tready(dmarx_tready_bclk[2]),
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.o3_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,3)), .o3_tlast(dmarx_tlast_bclk[3]), .o3_tvalid(dmarx_tvalid_bclk[3]), .o3_tready(dmarx_tready_bclk[3]),
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.o4_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,4)), .o4_tlast(dmarx_tlast_bclk[4]), .o4_tvalid(dmarx_tvalid_bclk[4]), .o4_tready(dmarx_tready_bclk[4]),
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.o5_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,5)), .o5_tlast(dmarx_tlast_bclk[5]), .o5_tvalid(dmarx_tvalid_bclk[5]), .o5_tready(dmarx_tready_bclk[5]),
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.o6_tdata(), .o6_tlast(), .o6_tvalid(), .o6_tready(1'b0), //Unused port
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.o7_tdata(), .o7_tlast(), .o7_tvalid(), .o7_tready(1'b0) //Unused port
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);
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genvar j;
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generate
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for (j=0; j<NUM_RX_STREAMS; j=j+1) begin: rx_dma_stuff_generator
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assign dmarx_samp_stb[j] = dmarx_tvalid_bclk[j] & dmarx_tready_bclk[j];
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assign dmarx_pkt_stb[j] = dmarx_samp_stb[j] & dmarx_tlast_bclk[j];
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cvita_chunker rx_dma_chunker (
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.clk(bus_clk), .reset(bus_rst), .clear(dmarx_clear[j]), .frame_size(`GET_FSIZE_BUS(dmarx_frame_size, j)),
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.i_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,j)), .i_tlast(dmarx_tlast_bclk[j]), .i_tvalid(dmarx_tvalid_bclk[j]), .i_tready(dmarx_tready_bclk[j]),
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.o_tdata(`GET_DMA_BUS(dmarx_tdata_pad,j)), .o_tlast(dmarx_tlast_pad[j]), .o_tvalid(dmarx_tvalid_pad[j]), .o_tready(dmarx_tready_pad[j]),
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.error(dmarx_error[j])
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);
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data_swapper_64 rx_data_swapper (
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.swap_lanes(`GET_SWAP_BUS(dmarx_swap,j)), .i_tdata(`GET_DMA_BUS(dmarx_tdata_pad,j)), .o_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j))
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);
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axi_fifo_2clk #(.WIDTH(DMA_STREAM_WIDTH), .SIZE(DMA_CLK_XING_FIFO_SIZE)) rx_dma_clock_crossing_fifo (
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.reset(bus_rst),
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.i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
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.o_aclk(ioport2_clk), .o_tdata(`GET_DMA_BUS(dmarx_tdata_iop2,j)), .o_tvalid(dmarx_tvalid_iop2[j]), .o_tready(dmarx_tready_iop2[j])
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);
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end
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endgenerate
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//
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//*******************************************************************************
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endmodule
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`undef GET_DMA_BUS
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`undef GET_FSIZE_BUS
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`undef GET_SWAP_BUS
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