849 lines
41 KiB
Verilog
849 lines
41 KiB
Verilog
`timescale 1ps / 1ps
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module x300_tb();
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/////////////////// START FROM XILINX TB ///////////////////////////
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//***************************************************************************
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// Traffic Gen related parameters
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//***************************************************************************
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parameter SIMULATION = "TRUE";
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parameter BL_WIDTH = 10;
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parameter PORT_MODE = "BI_MODE";
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parameter DATA_MODE = 4'b0010;
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parameter ADDR_MODE = 4'b0011;
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parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE";
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parameter EYE_TEST = "FALSE";
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// set EYE_TEST = "TRUE" to probe memory
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// signals. Traffic Generator will only
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// write to one single location and no
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// read transactions will be generated.
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parameter DATA_PATTERN = "DGEN_ALL";
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// For small devices, choose one only.
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// For large device, choose "DGEN_ALL"
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// "DGEN_HAMMER", "DGEN_WALKING1",
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// "DGEN_WALKING0","DGEN_ADDR","
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// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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parameter CMD_PATTERN = "CGEN_ALL";
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// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
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// "CGEN_SEQUENTIAL", "CGEN_ALL"
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parameter BEGIN_ADDRESS = 32'h00000000;
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parameter END_ADDRESS = 32'h00000fff;
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parameter PRBS_EADDR_MASK_POS = 32'hff000000;
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parameter SEL_VICTIM_LINE = 11;
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//***************************************************************************
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// The following parameters refer to width of various ports
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//***************************************************************************
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parameter BANK_WIDTH = 3;
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// # of memory Bank Address bits.
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parameter CK_WIDTH = 1;
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// # of CK/CK# outputs to memory.
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parameter COL_WIDTH = 10;
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// # of memory Column Address bits.
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parameter CS_WIDTH = 1;
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// # of unique CS outputs to memory.
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parameter nCS_PER_RANK = 1;
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// # of unique CS outputs per rank for phy
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parameter CKE_WIDTH = 1;
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// # of CKE outputs to memory.
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parameter DATA_BUF_ADDR_WIDTH = 5;
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parameter DQ_CNT_WIDTH = 5;
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// = ceil(log2(DQ_WIDTH))
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parameter DQ_PER_DM = 8;
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parameter DM_WIDTH = 4;
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// # of DM (data mask)
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parameter DQ_WIDTH = 32;
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// # of DQ (data)
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parameter DQS_WIDTH = 4;
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parameter DQS_CNT_WIDTH = 2;
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// = ceil(log2(DQS_WIDTH))
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parameter DRAM_WIDTH = 8;
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// # of DQ per DQS
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parameter ECC = "OFF";
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parameter nBANK_MACHS = 4;
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parameter RANKS = 1;
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// # of Ranks.
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parameter ODT_WIDTH = 1;
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// # of ODT outputs to memory.
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parameter ROW_WIDTH = 15;
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// # of memory Row Address bits.
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parameter ADDR_WIDTH = 29;
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// # = RANK_WIDTH + BANK_WIDTH
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// + ROW_WIDTH + COL_WIDTH;
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// Chip Select is always tied to low for
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// single rank devices
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parameter USE_CS_PORT = 1;
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// # = 1, When CS output is enabled
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// = 0, When CS output is disabled
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// If CS_N disabled, user must connect
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// DRAM CS_N input(s) to ground
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parameter USE_DM_PORT = 1;
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// # = 1, When Data Mask option is enabled
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// = 0, When Data Mask option is disbaled
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// When Data Mask option is disabled in
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// MIG Controller Options page, the logic
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// related to Data Mask should not get
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// synthesized
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parameter USE_ODT_PORT = 1;
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// # = 1, When ODT output is enabled
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// = 0, When ODT output is disabled
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//***************************************************************************
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// The following parameters are mode register settings
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//***************************************************************************
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parameter AL = "0";
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// DDR3 SDRAM:
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// Additive Latency (Mode Register 1).
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// # = "0", "CL-1", "CL-2".
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// DDR2 SDRAM:
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// Additive Latency (Extended Mode Register).
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parameter nAL = 0;
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// # Additive Latency in number of clock
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// cycles.
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parameter BURST_MODE = "8";
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// DDR3 SDRAM:
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// Burst Length (Mode Register 0).
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// # = "8", "4", "OTF".
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// DDR2 SDRAM:
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// Burst Length (Mode Register).
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// # = "8", "4".
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parameter BURST_TYPE = "SEQ";
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// DDR3 SDRAM: Burst Type (Mode Register 0).
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// DDR2 SDRAM: Burst Type (Mode Register).
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// # = "SEQ" - (Sequential),
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// = "INT" - (Interleaved).
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parameter CL = 7;
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// in number of clock cycles
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// DDR3 SDRAM: CAS Latency (Mode Register 0).
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// DDR2 SDRAM: CAS Latency (Mode Register).
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parameter CWL = 6;
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// in number of clock cycles
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// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
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// DDR2 SDRAM: Can be ignored
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parameter OUTPUT_DRV = "HIGH";
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// Output Driver Impedance Control (Mode Register 1).
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// # = "HIGH" - RZQ/7,
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// = "LOW" - RZQ/6.
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parameter RTT_NOM = "60";
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// RTT_NOM (ODT) (Mode Register 1).
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// # = "DISABLED" - RTT_NOM disabled,
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// = "120" - RZQ/2,
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// = "60" - RZQ/4,
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// = "40" - RZQ/6.
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parameter RTT_WR = "OFF";
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// RTT_WR (ODT) (Mode Register 2).
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// # = "OFF" - Dynamic ODT off,
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// = "120" - RZQ/2,
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// = "60" - RZQ/4,
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parameter ADDR_CMD_MODE = "1T" ;
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// # = "1T", "2T".
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parameter REG_CTRL = "OFF";
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// # = "ON" - RDIMMs,
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// = "OFF" - Components, SODIMMs, UDIMMs.
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parameter CA_MIRROR = "OFF";
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// C/A mirror opt for DDR3 dual rank
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//***************************************************************************
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// The following parameters are multiplier and divisor factors for PLLE2.
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// Based on the selected design frequency these parameters vary.
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//***************************************************************************
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parameter CLKIN_PERIOD = 10000;
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// Input Clock Period
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parameter CLKFBOUT_MULT = 10;
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// write PLL VCO multiplier
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parameter DIVCLK_DIVIDE = 1;
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// write PLL VCO divisor
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parameter CLKOUT0_DIVIDE = 2;
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// VCO output divisor for PLL output clock (CLKOUT0)
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parameter CLKOUT1_DIVIDE = 2;
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// VCO output divisor for PLL output clock (CLKOUT1)
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parameter CLKOUT2_DIVIDE = 32;
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// VCO output divisor for PLL output clock (CLKOUT2)
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parameter CLKOUT3_DIVIDE = 8;
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// VCO output divisor for PLL output clock (CLKOUT3)
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//***************************************************************************
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// Memory Timing Parameters. These parameters varies based on the selected
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// memory part.
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//***************************************************************************
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parameter tCKE = 5000;
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// memory tCKE paramter in pS
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parameter tFAW = 30000;
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// memory tRAW paramter in pS.
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parameter tRAS = 35000;
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// memory tRAS paramter in pS.
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parameter tRCD = 13750;
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// memory tRCD paramter in pS.
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parameter tREFI = 7800000;
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// memory tREFI paramter in pS.
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parameter tRFC = 300000;
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// memory tRFC paramter in pS.
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parameter tRP = 13750;
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// memory tRP paramter in pS.
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parameter tRRD = 6000;
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// memory tRRD paramter in pS.
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parameter tRTP = 7500;
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// memory tRTP paramter in pS.
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parameter tWTR = 7500;
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// memory tWTR paramter in pS.
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parameter tZQI = 128_000_000;
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// memory tZQI paramter in nS.
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parameter tZQCS = 64;
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// memory tZQCS paramter in clock cycles.
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//***************************************************************************
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// Simulation parameters
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//***************************************************************************
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parameter SIM_BYPASS_INIT_CAL = "FAST";
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// # = "SIM_INIT_CAL_FULL" - Complete
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// memory init &
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// calibration sequence
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// # = "SKIP" - Not supported
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// # = "FAST" - Complete memory init & use
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// abbreviated calib sequence
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//***************************************************************************
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// The following parameters varies based on the pin out entered in MIG GUI.
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// Do not change any of these parameters directly by editing the RTL.
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// Any changes required should be done through GUI and the design regenerated.
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//***************************************************************************
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parameter BYTE_LANES_B0 = 4'b1111;
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B1 = 4'b1110;
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B2 = 4'b0000;
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B3 = 4'b0000;
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B4 = 4'b0000;
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// Byte lanes used in an IO column.
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parameter DATA_CTL_B0 = 4'b1111;
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B1 = 4'b0000;
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B2 = 4'b0000;
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B3 = 4'b0000;
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B4 = 4'b0000;
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF;
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parameter PHY_1_BITLANES = 48'h3FF_FFF_C00_000;
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parameter PHY_2_BITLANES = 48'h000_000_000_000;
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// control/address/data pin mapping parameters
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parameter CK_BYTE_MAP
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= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13;
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parameter ADDR_MAP
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= 192'h000_139_138_137_136_135_134_133_132_131_130_129_128_127_126_12B;
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parameter BANK_MAP = 36'h12A_125_124;
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parameter CAS_MAP = 12'h122;
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parameter CKE_ODT_BYTE_MAP = 8'h00;
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parameter CKE_MAP = 96'h000_000_000_000_000_000_000_11B;
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parameter ODT_MAP = 96'h000_000_000_000_000_000_000_11A;
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parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_120;
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parameter PARITY_MAP = 12'h000;
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parameter RAS_MAP = 12'h123;
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parameter WE_MAP = 12'h121;
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parameter DQS_BYTE_MAP
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= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01_02_03;
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parameter DATA0_MAP = 96'h031_032_033_034_035_036_037_038;
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parameter DATA1_MAP = 96'h021_022_023_024_025_026_027_028;
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parameter DATA2_MAP = 96'h011_012_013_014_015_016_017_018;
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parameter DATA3_MAP = 96'h000_001_002_003_004_005_006_007;
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parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000;
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parameter MASK0_MAP = 108'h000_000_000_000_000_009_019_029_039;
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parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000;
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parameter SLOT_0_CONFIG = 8'b0000_0001;
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// Mapping of Ranks.
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parameter SLOT_1_CONFIG = 8'b0000_0000;
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// Mapping of Ranks.
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parameter MEM_ADDR_ORDER
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= "BANK_ROW_COLUMN";
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//***************************************************************************
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// IODELAY and PHY related parameters
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//***************************************************************************
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parameter IODELAY_HP_MODE = "ON";
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// to phy_top
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parameter IBUF_LPWR_MODE = "OFF";
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// to phy_top
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parameter DATA_IO_IDLE_PWRDWN = "ON";
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// # = "ON", "OFF"
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parameter DATA_IO_PRIM_TYPE = "HP_LP";
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// # = "HP_LP", "HR_LP", "DEFAULT"
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parameter USER_REFRESH = "OFF";
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parameter WRLVL = "ON";
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// # = "ON" - DDR3 SDRAM
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// = "OFF" - DDR2 SDRAM.
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parameter ORDERING = "NORM";
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// # = "NORM", "STRICT", "RELAXED".
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parameter CALIB_ROW_ADD = 16'h0000;
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// Calibration row address will be used for
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// calibration read and write operations
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parameter CALIB_COL_ADD = 12'h000;
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// Calibration column address will be used for
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// calibration read and write operations
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parameter CALIB_BA_ADD = 3'h0;
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// Calibration bank address will be used for
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// calibration read and write operations
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parameter TCQ = 100;
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//***************************************************************************
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// IODELAY and PHY related parameters
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//***************************************************************************
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parameter IODELAY_GRP = "IODELAY_MIG";
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// It is associated to a set of IODELAYs with
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// an IDELAYCTRL that have same IODELAY CONTROLLER
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// clock frequency.
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parameter SYSCLK_TYPE = "SINGLE_ENDED";
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// System clock type DIFFERENTIAL, SINGLE_ENDED,
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// NO_BUFFER
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parameter REFCLK_TYPE = "NO_BUFFER";
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// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
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// NO_BUFFER, USE_SYSTEM_CLOCK
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parameter RST_ACT_LOW = 1;
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// =1 for active low reset,
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// =0 for active high.
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parameter CAL_WIDTH = "HALF";
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parameter STARVE_LIMIT = 2;
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// # = 2,3,4.
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//***************************************************************************
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// Referece clock frequency parameters
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//***************************************************************************
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parameter REFCLK_FREQ = 200.0;
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// IODELAYCTRL reference clock frequency
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//***************************************************************************
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// System clock frequency parameters
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//***************************************************************************
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parameter tCK = 2000;
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// memory tCK paramter.
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// # = Clock Period in pS.
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parameter nCK_PER_CLK = 4;
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// # of memory CKs per fabric CLK
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//***************************************************************************
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// AXI4 Shim parameters
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//***************************************************************************
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parameter C_S_AXI_ID_WIDTH = 4;
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// Width of all master and slave ID signals.
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// # = >= 1.
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parameter C_S_AXI_ADDR_WIDTH = 32;
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// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
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// M_AXI_ARADDR for all SI/MI slots.
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// # = 32.
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parameter C_S_AXI_DATA_WIDTH = 128;
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// Width of WDATA and RDATA on SI slot.
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// Must be <= APP_DATA_WIDTH.
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// # = 32, 64, 128, 256.
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parameter C_MC_nCK_PER_CLK = 4;
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// Indicates whether to instatiate upsizer
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// Range: 0, 1
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parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1;
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// Indicates whether to instatiate upsizer
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// Range: 0, 1
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parameter C_RD_WR_ARB_ALGORITHM = "ROUND_ROBIN";
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// Indicates the Arbitration
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// Allowed values - "TDM", "ROUND_ROBIN",
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// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
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parameter C_S_AXI_REG_EN0 = 20'h00000;
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// C_S_AXI_REG_EN0[00] = Reserved
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// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
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// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
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// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
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// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
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parameter C_S_AXI_REG_EN1 = 20'h00000;
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// Instatiates register slices after the upsizer.
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// The type of register is specified for each channel
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// in a vector. 4 bits per channel are used.
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// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
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// Possible values for each channel are:
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//
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// 0 => BYPASS = The channel is just wired through the
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// module.
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// 1 => FWD = The master VALID and payload signals
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// are registrated.
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// 2 => REV = The slave ready signal is registrated
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// 3 => FWD_REV = Both FWD and REV
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// 4 => SLAVE_FWD = All slave side signals and master
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// VALID and payload are registrated.
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// 5 => SLAVE_RDY = All slave side signals and master
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// READY are registrated.
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// 6 => INPUTS = Slave and Master side inputs are
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// registrated.
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// 7 => ADDRESS = Optimized for address channel
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//***************************************************************************
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// Debug and Internal parameters
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//***************************************************************************
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parameter DEBUG_PORT = "OFF";
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// # = "ON" Enable debug signals/controls.
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// = "OFF" Disable debug signals/controls.
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//***************************************************************************
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// Debug and Internal parameters
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//***************************************************************************
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parameter DRAM_TYPE = "DDR3";
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//**************************************************************************//
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// Local parameters Declarations
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//**************************************************************************//
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localparam real TPROP_DQS = 0.00;
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// Delay for DQS signal during Write Operation
|
|
localparam real TPROP_DQS_RD = 0.00;
|
|
// Delay for DQS signal during Read Operation
|
|
localparam real TPROP_PCB_CTRL = 0.00;
|
|
// Delay for Address and Ctrl signals
|
|
localparam real TPROP_PCB_DATA = 0.00;
|
|
// Delay for data signal during Write operation
|
|
localparam real TPROP_PCB_DATA_RD = 0.00;
|
|
// Delay for data signal during Read operation
|
|
|
|
localparam MEMORY_WIDTH = 16;
|
|
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
|
|
|
|
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
|
|
localparam RESET_PERIOD = 200000; //in pSec
|
|
localparam real SYSCLK_PERIOD = tCK;
|
|
|
|
///////////////// END FROM XILINX TB //////////////////////////////////////////
|
|
|
|
wire [31:0] ddr3_dq; // Data pins. Input for Reads, Output for Writes.
|
|
wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads, Output for Writes.
|
|
wire [3:0] ddr3_dqs_p;
|
|
wire [14:0] ddr3_addr; // Address
|
|
wire [2:0] ddr3_ba; // Bank Address
|
|
wire ddr3_ras_n; // Row Address Strobe.
|
|
wire ddr3_cas_n; // Column address select
|
|
wire ddr3_we_n; // Write Enable
|
|
wire ddr3_reset_n; // SDRAM reset pin.
|
|
wire ddr3_ck_p; // Differential clock
|
|
wire ddr3_ck_n;
|
|
wire ddr3_cke; // Clock Enable
|
|
wire ddr3_cs_n; // Chip Select
|
|
wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26, [2] = LDM.U26, ...
|
|
wire ddr3_odt; // On-Die termination enable.
|
|
reg sys_clk_i; // 100MHz clock source to generate DDR3 clocking.
|
|
reg FPGA_CLK_p, FPGA_CLK_n;
|
|
reg FPGA_125MHz_CLK;
|
|
|
|
///////////////////////////////////////////////////////////
|
|
//
|
|
// 120MHz differential clock source
|
|
//
|
|
///////////////////////////////////////////////////////////
|
|
initial
|
|
begin
|
|
FPGA_CLK_p <= 0;
|
|
FPGA_CLK_n <= 1;
|
|
end
|
|
|
|
always #4000 begin
|
|
FPGA_CLK_p <= ~FPGA_CLK_p;
|
|
FPGA_CLK_n <= ~FPGA_CLK_n;
|
|
end
|
|
|
|
|
|
///////////////////////////////////////////////////////////
|
|
//
|
|
// 125MHz clock source
|
|
//
|
|
///////////////////////////////////////////////////////////
|
|
initial FPGA_125MHz_CLK <= 0;
|
|
|
|
always #4000 FPGA_125MHz_CLK <= ~FPGA_125MHz_CLK;
|
|
|
|
///////////////////////////////////////////////////////////
|
|
//
|
|
// 100MHz clock source for DDR3
|
|
//
|
|
///////////////////////////////////////////////////////////
|
|
initial
|
|
sys_clk_i <= 0;
|
|
|
|
always #5000 sys_clk_i = ~sys_clk_i;
|
|
|
|
///////////////////////////////////////////////////////////
|
|
//
|
|
// 2x 4Gb DDR3 SDRAMS x16
|
|
//
|
|
///////////////////////////////////////////////////////////
|
|
|
|
ddr3_model sdram0 (
|
|
.rst_n(ddr3_reset_n),
|
|
.ck(ddr3_ck_p),
|
|
.ck_n(ddr3_ck_n),
|
|
.cke(ddr3_cke),
|
|
.cs_n(ddr3_cs_n),
|
|
.ras_n(ddr3_ras_n),
|
|
.cas_n(ddr3_cas_n),
|
|
.we_n(ddr3_we_n),
|
|
.dm_tdqs(ddr3_dm[1:0]),
|
|
.ba(ddr3_ba),
|
|
.addr(ddr3_addr),
|
|
.dq(ddr3_dq[15:0]),
|
|
.dqs(ddr3_dqs_p[1:0]),
|
|
.dqs_n(ddr3_dqs_n[1:0]),
|
|
.tdqs_n(), // Unused on x16
|
|
.odt(ddr3_odt)
|
|
);
|
|
|
|
ddr3_model sdram1 (
|
|
.rst_n(ddr3_reset_n),
|
|
.ck(ddr3_ck_p),
|
|
.ck_n(ddr3_ck_n),
|
|
.cke(ddr3_cke),
|
|
.cs_n(ddr3_cs_n),
|
|
.ras_n(ddr3_ras_n),
|
|
.cas_n(ddr3_cas_n),
|
|
.we_n(ddr3_we_n),
|
|
.dm_tdqs(ddr3_dm[3:2]),
|
|
.ba(ddr3_ba),
|
|
.addr(ddr3_addr),
|
|
.dq(ddr3_dq[31:16]),
|
|
.dqs(ddr3_dqs_p[3:2]),
|
|
.dqs_n(ddr3_dqs_n[3:2]),
|
|
.tdqs_n(), // Unused on x16
|
|
.odt(ddr3_odt)
|
|
);
|
|
|
|
///////////////////////////////////////////////////////////
|
|
//
|
|
// DUT
|
|
//
|
|
///////////////////////////////////////////////////////////
|
|
|
|
x300 #
|
|
(
|
|
|
|
.SIMULATION (SIMULATION),
|
|
.BL_WIDTH (BL_WIDTH),
|
|
.PORT_MODE (PORT_MODE),
|
|
.DATA_MODE (DATA_MODE),
|
|
.ADDR_MODE (ADDR_MODE),
|
|
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
|
|
.EYE_TEST (EYE_TEST),
|
|
.DATA_PATTERN (DATA_PATTERN),
|
|
.CMD_PATTERN (CMD_PATTERN),
|
|
.BEGIN_ADDRESS (BEGIN_ADDRESS),
|
|
.END_ADDRESS (END_ADDRESS),
|
|
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
|
|
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
|
|
|
|
.BANK_WIDTH (BANK_WIDTH),
|
|
.CK_WIDTH (CK_WIDTH),
|
|
.COL_WIDTH (COL_WIDTH),
|
|
.CS_WIDTH (CS_WIDTH),
|
|
.nCS_PER_RANK (nCS_PER_RANK),
|
|
.CKE_WIDTH (CKE_WIDTH),
|
|
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
|
|
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
|
|
.DQ_PER_DM (DQ_PER_DM),
|
|
.DM_WIDTH (DM_WIDTH),
|
|
|
|
.DQ_WIDTH (DQ_WIDTH),
|
|
.DQS_WIDTH (DQS_WIDTH),
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
|
.ECC (ECC),
|
|
.nBANK_MACHS (nBANK_MACHS),
|
|
.RANKS (RANKS),
|
|
.ODT_WIDTH (ODT_WIDTH),
|
|
.ROW_WIDTH (ROW_WIDTH),
|
|
.ADDR_WIDTH (ADDR_WIDTH),
|
|
.USE_CS_PORT (USE_CS_PORT),
|
|
.USE_DM_PORT (USE_DM_PORT),
|
|
.USE_ODT_PORT (USE_ODT_PORT),
|
|
|
|
.AL (AL),
|
|
.nAL (nAL),
|
|
.BURST_MODE (BURST_MODE),
|
|
.BURST_TYPE (BURST_TYPE),
|
|
.CL (CL),
|
|
.CWL (CWL),
|
|
.OUTPUT_DRV (OUTPUT_DRV),
|
|
.RTT_NOM (RTT_NOM),
|
|
.RTT_WR (RTT_WR),
|
|
.ADDR_CMD_MODE (ADDR_CMD_MODE),
|
|
.REG_CTRL (REG_CTRL),
|
|
.CA_MIRROR (CA_MIRROR),
|
|
|
|
|
|
.CLKIN_PERIOD (CLKIN_PERIOD),
|
|
.CLKFBOUT_MULT (CLKFBOUT_MULT),
|
|
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
|
|
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
|
|
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
|
|
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
|
|
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
|
|
|
|
|
|
.tCKE (tCKE),
|
|
.tFAW (tFAW),
|
|
.tRAS (tRAS),
|
|
.tRCD (tRCD),
|
|
.tREFI (tREFI),
|
|
.tRFC (tRFC),
|
|
.tRP (tRP),
|
|
.tRRD (tRRD),
|
|
.tRTP (tRTP),
|
|
.tWTR (tWTR),
|
|
.tZQI (tZQI),
|
|
.tZQCS (tZQCS),
|
|
|
|
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
|
|
|
|
.BYTE_LANES_B0 (BYTE_LANES_B0),
|
|
.BYTE_LANES_B1 (BYTE_LANES_B1),
|
|
.BYTE_LANES_B2 (BYTE_LANES_B2),
|
|
.BYTE_LANES_B3 (BYTE_LANES_B3),
|
|
.BYTE_LANES_B4 (BYTE_LANES_B4),
|
|
.DATA_CTL_B0 (DATA_CTL_B0),
|
|
.DATA_CTL_B1 (DATA_CTL_B1),
|
|
.DATA_CTL_B2 (DATA_CTL_B2),
|
|
.DATA_CTL_B3 (DATA_CTL_B3),
|
|
.DATA_CTL_B4 (DATA_CTL_B4),
|
|
.PHY_0_BITLANES (PHY_0_BITLANES),
|
|
.PHY_1_BITLANES (PHY_1_BITLANES),
|
|
.PHY_2_BITLANES (PHY_2_BITLANES),
|
|
.CK_BYTE_MAP (CK_BYTE_MAP),
|
|
.ADDR_MAP (ADDR_MAP),
|
|
.BANK_MAP (BANK_MAP),
|
|
.CAS_MAP (CAS_MAP),
|
|
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
|
|
.CKE_MAP (CKE_MAP),
|
|
.ODT_MAP (ODT_MAP),
|
|
.CS_MAP (CS_MAP),
|
|
.PARITY_MAP (PARITY_MAP),
|
|
.RAS_MAP (RAS_MAP),
|
|
.WE_MAP (WE_MAP),
|
|
.DQS_BYTE_MAP (DQS_BYTE_MAP),
|
|
.DATA0_MAP (DATA0_MAP),
|
|
.DATA1_MAP (DATA1_MAP),
|
|
.DATA2_MAP (DATA2_MAP),
|
|
.DATA3_MAP (DATA3_MAP),
|
|
.DATA4_MAP (DATA4_MAP),
|
|
.DATA5_MAP (DATA5_MAP),
|
|
.DATA6_MAP (DATA6_MAP),
|
|
.DATA7_MAP (DATA7_MAP),
|
|
.DATA8_MAP (DATA8_MAP),
|
|
.DATA9_MAP (DATA9_MAP),
|
|
.DATA10_MAP (DATA10_MAP),
|
|
.DATA11_MAP (DATA11_MAP),
|
|
.DATA12_MAP (DATA12_MAP),
|
|
.DATA13_MAP (DATA13_MAP),
|
|
.DATA14_MAP (DATA14_MAP),
|
|
.DATA15_MAP (DATA15_MAP),
|
|
.DATA16_MAP (DATA16_MAP),
|
|
.DATA17_MAP (DATA17_MAP),
|
|
.MASK0_MAP (MASK0_MAP),
|
|
.MASK1_MAP (MASK1_MAP),
|
|
.SLOT_0_CONFIG (SLOT_0_CONFIG),
|
|
.SLOT_1_CONFIG (SLOT_1_CONFIG),
|
|
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
|
|
|
|
.IODELAY_HP_MODE (IODELAY_HP_MODE),
|
|
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
|
|
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
|
|
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
|
|
.USER_REFRESH (USER_REFRESH),
|
|
.WRLVL (WRLVL),
|
|
.ORDERING (ORDERING),
|
|
.CALIB_ROW_ADD (CALIB_ROW_ADD),
|
|
.CALIB_COL_ADD (CALIB_COL_ADD),
|
|
.CALIB_BA_ADD (CALIB_BA_ADD),
|
|
.TCQ (TCQ),
|
|
|
|
|
|
.IODELAY_GRP (IODELAY_GRP),
|
|
.SYSCLK_TYPE (SYSCLK_TYPE),
|
|
.REFCLK_TYPE (REFCLK_TYPE),
|
|
.DRAM_TYPE (DRAM_TYPE),
|
|
.CAL_WIDTH (CAL_WIDTH),
|
|
.STARVE_LIMIT (STARVE_LIMIT),
|
|
|
|
|
|
.REFCLK_FREQ (REFCLK_FREQ),
|
|
|
|
|
|
.tCK (tCK),
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
|
|
|
|
|
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
|
|
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
|
|
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
|
|
.C_MC_nCK_PER_CLK (C_MC_nCK_PER_CLK),
|
|
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
|
|
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
|
|
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
|
|
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
|
|
|
|
.DEBUG_PORT (DEBUG_PORT),
|
|
|
|
.RST_ACT_LOW (RST_ACT_LOW)
|
|
)
|
|
|
|
x300 (
|
|
.FPGA_CLK_p(FPGA_CLK_p),
|
|
.FPGA_CLK_n(FPGA_CLK_n),
|
|
.FPGA_125MHz_CLK(FPGA_125MHz_CLK),
|
|
// 1Gb SFP signals
|
|
.SFP_CLK_AC_p(),
|
|
.SFP_CLK_AC_n(),
|
|
.SFP_RX_p(),
|
|
.SFP_RX_n(),
|
|
.SFP_TX_p(),
|
|
.SFP_TX_n(),
|
|
// DDR3 I/F
|
|
.ddr3_addr(ddr3_addr),
|
|
.ddr3_ba(ddr3_ba),
|
|
.ddr3_ras_n(ddr3_ras_n),
|
|
.ddr3_cas_n(ddr3_cas_n),
|
|
.ddr3_we_n(ddr3_we_n),
|
|
.ddr3_reset_n(ddr3_reset_n),
|
|
.ddr3_ck_p(ddr3_ck_p),
|
|
.ddr3_ck_n(ddr3_ck_n),
|
|
.ddr3_cke(ddr3_cke),
|
|
.ddr3_cs_n(ddr3_cs_n),
|
|
.ddr3_dm(ddr3_dm),
|
|
.ddr3_odt(ddr3_odt),
|
|
.ddr3_dq(ddr3_dq),
|
|
.ddr3_dqs_n(ddr3_dqs_n),
|
|
.ddr3_dqs_p(ddr3_dqs_p),
|
|
.sys_clk_i(sys_clk_i),
|
|
// ADC0
|
|
.DB0_ADC_DCLK_P(), .DB0_ADC_DCLK_N(),
|
|
.DB0_ADC_DA0_P(), .DB0_ADC_DA0_N(), .DB0_ADC_DB0_P(), .DB0_ADC_DB0_N(),
|
|
.DB0_ADC_DA1_P(), .DB0_ADC_DA1_N(), .DB0_ADC_DB1_P(), .DB0_ADC_DB1_N(),
|
|
.DB0_ADC_DA2_P(), .DB0_ADC_DA2_N(), .DB0_ADC_DB2_P(), .DB0_ADC_DB2_N(),
|
|
.DB0_ADC_DA3_P(), .DB0_ADC_DA3_N(), .DB0_ADC_DB3_P(), .DB0_ADC_DB3_N(),
|
|
.DB0_ADC_DA4_P(), .DB0_ADC_DA4_N(), .DB0_ADC_DB4_P(), .DB0_ADC_DB4_N(),
|
|
.DB0_ADC_DA5_P(), .DB0_ADC_DA5_N(), .DB0_ADC_DB5_P(), .DB0_ADC_DB5_N(),
|
|
.DB0_ADC_DA6_P(), .DB0_ADC_DA6_N(), .DB0_ADC_DB6_P(), .DB0_ADC_DB6_N(),
|
|
|
|
// ADC1
|
|
|
|
.DB1_ADC_DCLK_P(), .DB1_ADC_DCLK_N(),
|
|
.DB1_ADC_DA0_P(), .DB1_ADC_DA0_N(), .DB1_ADC_DB0_P(), .DB1_ADC_DB0_N(),
|
|
.DB1_ADC_DA1_P(), .DB1_ADC_DA1_N(), .DB1_ADC_DB1_P(), .DB1_ADC_DB1_N(),
|
|
.DB1_ADC_DA2_P(), .DB1_ADC_DA2_N(), .DB1_ADC_DB2_P(), .DB1_ADC_DB2_N(),
|
|
.DB1_ADC_DA3_P(), .DB1_ADC_DA3_N(), .DB1_ADC_DB3_P(), .DB1_ADC_DB3_N(),
|
|
.DB1_ADC_DA4_P(), .DB1_ADC_DA4_N(), .DB1_ADC_DB4_P(), .DB1_ADC_DB4_N(),
|
|
.DB1_ADC_DA5_P(), .DB1_ADC_DA5_N(), .DB1_ADC_DB5_P(), .DB1_ADC_DB5_N(),
|
|
.DB1_ADC_DA6_P(), .DB1_ADC_DA6_N(), .DB1_ADC_DB6_P(), .DB1_ADC_DB6_N(),
|
|
|
|
// DAC0
|
|
.DB0_DAC_DCI_P(), .DB0_DAC_DCI_N(),
|
|
.DB0_DAC_FRAME_P(), .DB0_DAC_FRAME_N(),
|
|
.DB0_DAC_D0_P(), .DB0_DAC_D0_N(), .DB0_DAC_D1_P(), .DB0_DAC_D1_N(),
|
|
.DB0_DAC_D2_P(), .DB0_DAC_D2_N(), .DB0_DAC_D3_P(), .DB0_DAC_D3_N(),
|
|
.DB0_DAC_D4_P(), .DB0_DAC_D4_N(), .DB0_DAC_D5_P(), .DB0_DAC_D5_N(),
|
|
.DB0_DAC_D6_P(), .DB0_DAC_D6_N(), .DB0_DAC_D7_P(), .DB0_DAC_D7_N(),
|
|
.DB0_DAC_ENABLE(),
|
|
|
|
// DAC1
|
|
.DB1_DAC_DCI_P(), .DB1_DAC_DCI_N(),
|
|
.DB1_DAC_FRAME_P(), .DB1_DAC_FRAME_N(),
|
|
.DB1_DAC_D0_P(), .DB1_DAC_D0_N(), .DB1_DAC_D1_P(), .DB1_DAC_D1_N(),
|
|
.DB1_DAC_D2_P(), .DB1_DAC_D2_N(), .DB1_DAC_D3_P(), .DB1_DAC_D3_N(),
|
|
.DB1_DAC_D4_P(), .DB1_DAC_D4_N(), .DB1_DAC_D5_P(), .DB1_DAC_D5_N(),
|
|
.DB1_DAC_D6_P(), .DB1_DAC_D6_N(), .DB1_DAC_D7_P(), .DB1_DAC_D7_N(),
|
|
.DB1_DAC_ENABLE(),
|
|
|
|
// Daughter Board 0 - SPI
|
|
.DB0_SCLK(), .DB0_MOSI(),
|
|
.DB0_ADC_SEN(), .DB0_DAC_SEN(), .DB0_TX_SEN(), .DB0_RX_SEN(),
|
|
.DB0_RX_LSADC_SEN(), .DB0_RX_LSDAC_SEN(), .DB0_TX_LSADC_SEN(), .DB0_TX_LSDAC_SEN(),
|
|
.DB0_RX_LSADC_MISO(), .DB0_RX_MISO(), .DB0_TX_LSADC_MISO(), .DB0_TX_MISO(),
|
|
|
|
// Daughter Board1 - SPI
|
|
.DB1_SCLK(), .DB1_MOSI(),
|
|
.DB1_ADC_SEN(), .DB1_DAC_SEN(), .DB1_TX_SEN(), .DB1_RX_SEN(),
|
|
.DB1_RX_LSADC_SEN(), .DB1_RX_LSDAC_SEN(), .DB1_TX_LSADC_SEN(), .DB1_TX_LSDAC_SEN(),
|
|
.DB1_RX_LSADC_MISO(), .DB1_RX_MISO(), .DB1_TX_LSADC_MISO(), .DB1_TX_MISO(),
|
|
|
|
// DaughterBoard
|
|
.DB_DAC_SCLK(), .DB_DAC_MOSI(),
|
|
.DB_ADC_RESET(), .DB_DAC_RESET(),
|
|
|
|
// SFP+ I2C
|
|
.SFPP_SCL(), .SFPP_SDA(),
|
|
|
|
// Debug
|
|
.DebugClkIn(),
|
|
.DebugClkOut(),
|
|
.DebugIo(),
|
|
|
|
// Front Panel
|
|
.FrontPanelGpio(),
|
|
.LED_ACT(), .LED_LINK(),
|
|
.LED_PPS(), .LED_REFLOCK(),
|
|
.LED_RX1_RX(), .LED_RX2_RX(),
|
|
.LED_TXRX1_RX(), .LED_TXRX1_TX(),
|
|
.LED_TXRX2_RX(), .LED_TXRX2_TX(),
|
|
|
|
// GPIO
|
|
.DB0_TX_IO(),
|
|
.DB0_RX_IO(),
|
|
.DB1_TX_IO(),
|
|
.DB1_RX_IO(),
|
|
|
|
// Clocking
|
|
.AD9510Status(), .AD9510Function(),
|
|
.AD9510_SEN(), .AD9510_MOSI(), .AD9510_SCLK(), .AD9510_MISO(),
|
|
.ClockRefSelect(),
|
|
.GPS_SER_IN(), .GPS_SER_OUT(),
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.GPS_PPS_OUT(), .EXT_PPS_IN(),
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.MIMO_TIME_IN_P(), .MIMO_TIME_IN_N(),
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.MIMO_TIME_OUT_P(), .MIMO_TIME_OUT_N(),
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// SFP+ contorl/status
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.SFPP_ModAbs(), .SFPP_RxLOS(), .SFPP_TxFault(),
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.SFPP_RS0(), .SFPP_RS1(), .SFPP_TxDisable() // These are actually open drain outputs
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);
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endmodule // x300_tb
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