149 lines
4.5 KiB
Verilog
149 lines
4.5 KiB
Verilog
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module gige_phy_mdio
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(input reset,
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input independent_clock,
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input sfp_clk,
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input SFP_RX_p,
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input SFP_RX_n,
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output SFP_TX_p,
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output SFP_TX_n,
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output gmii_clk,
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input [7:0] gmii_txd,
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input gmii_tx_en,
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input gmii_tx_er,
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output [7:0] gmii_rxd,
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output gmii_rx_dv,
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output gmii_rx_er,
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output [31:0] misc_debug,
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output [15:0] int_data,
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output [15:0] status_vector,
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// MDIO signals
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input [4:0] prtad,
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input mdc,
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input mdio_i,
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output mdio_o,
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output mdio_t
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);
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wire mmcm_locked, mmcm_reset, resetdone, clkfbout;
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wire userclk, userclk2;
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wire txoutclk, txoutclk_bufg;
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assign gmii_clk = userclk2; // 125 MHz
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// Route txoutclk input through a BUFG
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// FIXME is this really necessary? It seems wasteful.
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BUFG bufg_txoutclk (.I (txoutclk), .O (txoutclk_bufg));
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// This 62.5MHz clock is placed onto global clock routing and is then used
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// for tranceiver TXUSRCLK/RXUSRCLK.
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BUFG bufg_userclk (.I (clkout1), .O (userclk));
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// This 125MHz clock is placed onto global clock routing and is then used
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// to clock all Ethernet core logic.
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BUFG bufg_userclk2 (.I (clkout0), .O (userclk2));
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// The GT transceiver provides a 62.5MHz clock to the FPGA fabric. This is
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// routed to an MMCM module where it is used to create phase and frequency
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// related 62.5MHz and 125MHz clock sources
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MMCME2_ADV #
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(.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT_F (16.000),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (8.000),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.5),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (16),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.5),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (16.0),
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.REF_JITTER1 (0.010)
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) mmcm_adv_inst
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(// Output clocks
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.CLKFBOUT (clkfbout),
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.CLKFBOUTB (),
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.CLKOUT0 (clkout0),
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.CLKOUT0B (),
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.CLKOUT1 (clkout1),
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.CLKOUT1B (),
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.CLKOUT2 (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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// Input clock control
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.CLKFBIN (clkfbout),
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.CLKIN1 (txoutclk_bufg),
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.CLKIN2 (1'b0),
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// Tied to always select the primary input clock
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.CLKINSEL (1'b1),
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// Ports for dynamic reconfiguration
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.DADDR (7'h0),
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.DCLK (1'b0),
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.DEN (1'b0),
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.DI (16'h0),
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.DO (),
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.DRDY (),
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.DWE (1'b0),
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// Ports for dynamic phase shift
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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// Other control and status signals
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.LOCKED (mmcm_locked),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_reset)
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);
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assign mmcm_reset = reset | ~resetdone;
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gige_sfp_mdio_block gige_sfp_mdio_block
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(
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.gtrefclk (sfp_clk),
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.txp (SFP_TX_p),
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.txn (SFP_TX_n),
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.rxp (SFP_RX_p),
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.rxn (SFP_RX_n),
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.txoutclk (txoutclk),
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.resetdone (resetdone),
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.mmcm_locked (mmcm_locked),
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.userclk (userclk),
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.userclk2 (userclk2),
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.independent_clock_bufg(independent_clock),
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.pma_reset (reset),
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.gmii_txd (gmii_txd),
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.gmii_tx_en (gmii_tx_en),
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.gmii_tx_er (gmii_tx_er),
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.gmii_rxd (gmii_rxd),
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.gmii_rx_dv (gmii_rx_dv),
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.gmii_rx_er (gmii_rx_er),
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.gmii_isolate (), // Unused
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.mdc (mdc),
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.mdio_i (mdio_i),
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.mdio_o (mdio_o),
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.mdio_t (mdio_t),
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.phyad (prtad),
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.configuration_vector (5'b00000),
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.configuration_valid (1'b1), //default
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.status_vector (status_vector),
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.reset (reset),
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.signal_detect (1'b1)
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);
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endmodule // gige_phy
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