71 lines
1.2 KiB
Verilog
71 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
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module gen_ddrlvds_tb();
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wire GSR, GTS;
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glbl glbl( );
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reg clk = 1;
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reg reset = 1;
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reg tx_strobe = 0;
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always #100 clk = ~clk;
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always #200 tx_strobe = ~tx_strobe;
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initial $dumpfile("gen_ddrlvds_tb.vcd");
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initial $dumpvars(0,gen_ddrlvds_tb);
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wire [7:0] pins_p, pins_n;
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wire frame_p, frame_n;
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wire clk_p, clk_n;
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reg [7:0] count;
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wire [15:0] i = {4'hA,count};
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wire [15:0] q = {4'hB,count};
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initial
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begin
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#10000 reset = 0;
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BURST(4);
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BURST(5);
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#2000;
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$finish;
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end
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task BURST;
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input [7:0] len;
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begin
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// tx_strobe <= 0;
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count <= 0;
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@(posedge clk);
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@(posedge clk);
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repeat(len)
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begin
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// tx_strobe <= 1;
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@(posedge clk);
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// tx_strobe <= 0;
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@(posedge clk);
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count <= count + 1;
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end
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// tx_strobe <= 0;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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end
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endtask // BURST
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gen_ddrlvds gen_ddrlvds
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(.rst(reset),
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.tx_clk_p(clk_p), .tx_clk_n(clk_n),
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.tx_frame_p(frame_p), .tx_frame_n(frame_n),
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.tx_d_p(pins_p), .tx_d_n(pins_n),
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.tx_clk(clk), .tx_strobe(tx_strobe),
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.i(i), .q(q)
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);
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endmodule // gen_ddrlvds_tb
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