Files
b210-k7-fpga/top/x300/gen_ddrlvds_tb.build
T
Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00

21 lines
401 B
INI
Executable File

#!/bin/sh
rm -rf isim*
rm -rf gen_ddrlvds_tb
rm -rf fuse*
\
# --sourcelibdir ../../models \
vlogcomp \
--sourcelibext .v \
--sourcelibdir ../../coregen \
--sourcelibdir ../../control_lib \
--sourcelibdir . \
--sourcelibdir $XILINX/verilog/src \
--sourcelibdir $XILINX/verilog/src/unisims \
--work work \
gen_ddrlvds_tb.v
fuse -o gen_ddrlvds_tb gen_ddrlvds_tb