102 lines
2.9 KiB
Verilog
102 lines
2.9 KiB
Verilog
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module gen_ddrlvds
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(
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// 2X Radio clock
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input tx_clk_2x,
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// 1X Radio Clock
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input tx_clk_1x,
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// Reset signal synchronous to radio clock
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input reset,
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// Source synchronous differential clocks to DAC
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output tx_clk_2x_p,
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output tx_clk_2x_n,
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// Differential frame sync to DAC
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output tx_frame_p,
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output tx_frame_n,
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// Differential byte wide data to DAC.
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// Alternates I[15:8],I[7:0],Q[15:8],Q[7:0]
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output [7:0] tx_d_p,
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output [7:0] tx_d_n,
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// Input data
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input [15:0] i,
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input [15:0] q,
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// Rising edge sampled on sync_dacs triggers frame sync sequence
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input sync_dacs
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);
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reg [15:0] i_reg, q_reg;
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reg [15:0] i_2x, q_2x;
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reg phase, phase_2x;
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reg rising_edge;
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wire [15:0] i_and_q_2x;
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reg sync_2x;
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genvar z;
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wire [7:0] tx_int;
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wire tx_clk_2x_int;
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wire tx_frame_int;
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(* keep = "true", max_fanout = 10 *) wire phase_eq_phase2x = (phase == phase_2x);
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always @(posedge tx_clk_1x)
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if (reset)
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phase <= 1'b0;
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else
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phase <= ~phase;
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//
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// Pipeline input data so that 1x to 2x clock domain jump includes no logic external to this module.
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//
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always @(posedge tx_clk_1x)
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begin
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i_reg <= i;
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q_reg <= q;
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end
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always @(posedge tx_clk_2x)
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begin
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// Move 1x data to 2x domain, mostly just to add pipeline regs
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// for timing closure.
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i_2x <= i_reg;
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q_2x <= q_reg;
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// Sample phase to determine when 1x clock edges occur.
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// To sync multiple AD9146 DAC's an extended assertion of FRAME is required,
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// when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME,
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// also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for.
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sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
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rising_edge <= (phase_eq_phase2x && ~sync_2x);
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phase_2x <= phase;
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end
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// Interleave I and Q as SDR signals
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assign i_and_q_2x = rising_edge ? q_2x : i_2x;
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generate
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for(z = 0; z < 8; z = z + 1)
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begin : gen_pins
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OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z]));
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr
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(.Q(tx_int[z]), .C(tx_clk_2x),
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.CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0));
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end
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endgenerate
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// Generate framing signal to identify I and Q
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OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n));
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame
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(.Q(tx_frame_int), .C(tx_clk_2x),
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.CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0));
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// Source synchronous clk
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OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n));
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk
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(.Q(tx_clk_2x_int), .C(tx_clk_2x),
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.CE(1'b1), .D1(1'b1), .D2(1'b0), .S(1'b0), .R(1'b0));
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endmodule // gen_ddrlvds
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