80 lines
4.9 KiB
Verilog
80 lines
4.9 KiB
Verilog
/*******************************************************************************
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* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
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* *
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* This file contains confidential and proprietary information *
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* of Xilinx, Inc. and is protected under U.S. and *
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* international copyright and other intellectual property *
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* laws. *
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* *
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* DISCLAIMER *
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* This disclaimer is not a license and does not grant any *
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* rights to the materials distributed herewith. Except as *
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* otherwise provided in a valid license issued to you by *
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* Xilinx, and to the maximum extent permitted by applicable *
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* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
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* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
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* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
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* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
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* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
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* (2) Xilinx shall not be liable (whether in contract or tort, *
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* including negligence, or under any other theory of *
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* liability) for any loss or damage of any kind or nature *
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* related to, arising under or in connection with these *
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* materials, including for any direct, or any indirect, *
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* special, incidental, or consequential loss or damage *
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* (including loss of data, profits, goodwill, or any type of *
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* loss or damage suffered as a result of any action brought *
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* by a third party) even if such damage or loss was *
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* reasonably foreseeable or Xilinx had been advised of the *
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* possibility of the same. *
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* *
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* CRITICAL APPLICATIONS *
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* Xilinx products are not designed or intended to be fail- *
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* safe, or for use in any application requiring fail-safe *
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* performance, such as life-support or safety devices or *
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* systems, Class III medical devices, nuclear facilities, *
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* applications related to the deployment of airbags, or any *
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* other applications that could lead to death, personal *
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* injury, or severe property or environmental damage *
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* (individually and collectively, "Critical *
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* Applications"). Customer assumes the sole risk and *
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* liability of any use of Xilinx products in Critical *
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* Applications, subject only to applicable laws and *
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* regulations governing limitations on product liability. *
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* *
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
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* PART OF THIS FILE AT ALL TIMES. *
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*******************************************************************************/
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// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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hbint2 YourInstanceName (
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.sclr(sclr), // input sclr
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.clk(clk), // input clk
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.ce(ce), // input ce
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.nd(nd), // input nd
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.coef_ld(coef_ld), // input coef_ld
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.coef_we(coef_we), // input coef_we
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.coef_din(coef_din), // input [17 : 0] coef_din
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.rfd(rfd), // output rfd
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.rdy(rdy), // output rdy
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.data_valid(data_valid), // output data_valid
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.din_1(din_1), // input [23 : 0] din_1
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.din_2(din_2), // input [23 : 0] din_2
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.dout_1(dout_1), // output [46 : 0] dout_1
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.dout_2(dout_2)); // output [46 : 0] dout_2
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file hbint2.v when simulating
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// the core, hbint2. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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