103 lines
2.9 KiB
Plaintext
103 lines
2.9 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.4
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# Date: Wed Dec 4 21:33:01 2013
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:fir_compiler:5.0
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc7k325t
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SET devicefamily = kintex7
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ffg900
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT FIR_Compiler family Xilinx,_Inc. 5.0
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# END Select
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# BEGIN Parameters
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CSET allow_rounding_approximation=false
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CSET bestprecision=false
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CSET chan_in_adv=0
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CSET clock_frequency=200
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CSET coefficient_buffer_type=Automatic
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CSET coefficient_file=./hb47.coe
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CSET coefficient_fractional_bits=0
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CSET coefficient_reload=true
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CSET coefficient_sets=1
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CSET coefficient_sign=Signed
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CSET coefficient_structure=Half_Band
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CSET coefficient_width=18
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CSET coefficientsource=COE_File
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CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
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CSET columnconfig=4
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CSET component_name=hbdec2
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CSET data_buffer_type=Automatic
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CSET data_fractional_bits=0
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CSET data_sign=Signed
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CSET data_width=24
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CSET decimation_rate=2
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CSET displayreloadorder=false
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CSET filter_architecture=Systolic_Multiply_Accumulate
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CSET filter_selection=1
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CSET filter_type=Decimation
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CSET gui_behaviour=Coregen
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CSET hardwareoversamplingrate=1
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CSET has_ce=true
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CSET has_data_valid=true
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CSET has_nd=true
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CSET has_sclr=true
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CSET input_buffer_type=Automatic
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CSET inter_column_pipe_length=4
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CSET interpolation_rate=1
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CSET multi_column_support=Disabled
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CSET number_channels=1
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CSET number_paths=2
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CSET optimization_goal=Area
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CSET output_buffer_type=Automatic
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CSET output_rounding_mode=Full_Precision
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CSET output_width=47
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CSET passband_max=0.5
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CSET passband_min=0.0
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CSET preference_for_other_storage=Automatic
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CSET quantization=Integer_Coefficients
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CSET rate_change_type=Integer
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CSET ratespecification=Frequency_Specification
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CSET registered_output=true
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CSET sample_frequency=100
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CSET sampleperiod=1
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CSET sclr_deterministic=true
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CSET stopband_max=1.0
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CSET stopband_min=0.5
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CSET usechan_in_adv=false
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CSET zero_pack_factor=1
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-12-18T05:23:34Z
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# END Extra information
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GENERATE
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# CRC: b27c3487
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