50 lines
1.8 KiB
Plaintext
50 lines
1.8 KiB
Plaintext
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The design files are located at
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/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen:
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- ddr3_interface.veo:
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veo template file containing code that can be used as a model
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for instantiating a CORE Generator module in a HDL design.
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- ddr3_interface.xco:
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CORE Generator input file containing the parameters used to
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regenerate a core.
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- ddr3_interface_flist.txt:
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Text file listing all of the output files produced when a customized
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core was generated in the CORE Generator.
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- ddr3_interface_readme.txt:
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Text file indicating the files generated and how they are used.
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- ddr3_interface_xmdf.tcl:
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ISE Project Navigator interface file. ISE uses this file to determine
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how the files output by CORE Generator for the core can be integrated
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into your ISE project.
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- ddr3_interface.csv:
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Includes the pin out information which is used as support file
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for PlanAhead.
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- ddr3_interface.gise and ddr3_interface.xise:
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ISE Project Navigator support files. These are generated files and
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should not be edited directly.
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- ddr3_interface directory.
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In the ddr3_interface directory, three folders are created:
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- docs:
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This folder contains MIG user guide.
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- example_design:
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This folder includes script files to implement and simulate the design.
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This includes the traffic generator RTL modules and example_top module.
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- user_design:
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This folder includes the all RTL modules of controller, phy and
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user interface RTL modules. UCF file is provided.
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The example_design and user_design folders contain several other folders
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and files. All these output folders are discussed in more detail in
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MIG user guide (ug586_7Series_MIS.pdf) located in docs folder.
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