648 lines
44 KiB
XML
648 lines
44 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="10"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="10"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="10"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="11"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="12"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="12"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="12"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="13"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="13"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="15"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="16"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="17"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="17"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="17"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="18"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="18"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="18"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="21"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="21"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="24"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="24"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="24"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="25"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="25"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="26"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="26"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="26"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="28"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="28"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="28"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="29"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="29"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="29"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="30"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="30"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="30"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="31"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="31"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="31"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="32"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="32"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="32"/>
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</file>
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<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v" xil_pn:type="FILE_VERILOG">
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|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="67"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="67"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="69"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="69"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="69"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="70"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="70"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="70"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="71"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="71"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="71"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="72"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="72"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="73"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="73"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="73"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="74"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="74"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="74"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="75"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="75"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="76"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="76"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="76"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="78"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="78"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="78"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="79"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="79"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="79"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="80"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="80"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="80"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="81"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="81"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="81"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_top.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="82"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="82"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="82"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v" xil_pn:type="FILE_VERILOG">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
|
|
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="83"/>
|
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="83"/>
|
|
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="83"/>
|
|
</file>
|
|
<file xil_pn:name="ddr3_32bit/user_design/constraints/ddr3_32bit.ucf" xil_pn:type="FILE_UCF">
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
|
</file>
|
|
</files>
|
|
|
|
<properties>
|
|
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Top" xil_pn:value="Module|ddr3_32bit" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Top File" xil_pn:value="ddr3_32bit/user_design/rtl/ddr3_32bit.v" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ddr3_32bit" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
|
<!-- -->
|
|
<!-- The following properties are for internal use only. These should not be modified.-->
|
|
<!-- -->
|
|
<property xil_pn:name="PROP_DesignName" xil_pn:value="ddr3_32bit" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-24T15:58:29" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CD4EFC67324928C6B147BF32D10EC298" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
|
</properties>
|
|
|
|
<bindings>
|
|
<binding xil_pn:location="/ddr3_32bit" xil_pn:name="ddr3_32bit/user_design/constraints/ddr3_32bit.ucf"/>
|
|
</bindings>
|
|
|
|
<libraries/>
|
|
|
|
<autoManagedFiles>
|
|
<!-- The following files are identified by `include statements in verilog -->
|
|
<!-- source files and are automatically managed by Project Navigator. -->
|
|
<!-- -->
|
|
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
|
<!-- project is analyzed based on files automatically identified as -->
|
|
<!-- include files. -->
|
|
</autoManagedFiles>
|
|
|
|
</project>
|