90 lines
5.6 KiB
Verilog
90 lines
5.6 KiB
Verilog
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2013 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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/*******************************************************************************
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* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *
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* *
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* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
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* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
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* direct drop-in replacement. It should be used in all new Xilinx *
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* designs. The core supports RAM and ROM functions over a wide range of *
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* widths and depths. Use this core to generate block memories with *
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* symmetric or asymmetric read and write port widths, as well as cores *
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* which can perform simultaneous write operations to separate *
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* locations, and simultaneous read operations from the same location. *
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* For more information on differences in interface and feature support *
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* between this core and the Dual Port Block Memory and Single Port *
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* Block Memory LogiCOREs, please consult the data sheet. *
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*******************************************************************************/
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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axi4_bram_1kx64 your_instance_name (
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.s_aclk(s_aclk), // input s_aclk
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.s_aresetn(s_aresetn), // input s_aresetn
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.s_axi_awid(s_axi_awid), // input [0 : 0] s_axi_awid
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.s_axi_awaddr(s_axi_awaddr), // input [31 : 0] s_axi_awaddr
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.s_axi_awlen(s_axi_awlen), // input [7 : 0] s_axi_awlen
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.s_axi_awsize(s_axi_awsize), // input [2 : 0] s_axi_awsize
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.s_axi_awburst(s_axi_awburst), // input [1 : 0] s_axi_awburst
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.s_axi_awvalid(s_axi_awvalid), // input s_axi_awvalid
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.s_axi_awready(s_axi_awready), // output s_axi_awready
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.s_axi_wdata(s_axi_wdata), // input [63 : 0] s_axi_wdata
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.s_axi_wstrb(s_axi_wstrb), // input [7 : 0] s_axi_wstrb
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.s_axi_wlast(s_axi_wlast), // input s_axi_wlast
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.s_axi_wvalid(s_axi_wvalid), // input s_axi_wvalid
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.s_axi_wready(s_axi_wready), // output s_axi_wready
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.s_axi_bid(s_axi_bid), // output [0 : 0] s_axi_bid
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.s_axi_bresp(s_axi_bresp), // output [1 : 0] s_axi_bresp
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.s_axi_bvalid(s_axi_bvalid), // output s_axi_bvalid
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.s_axi_bready(s_axi_bready), // input s_axi_bready
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.s_axi_arid(s_axi_arid), // input [0 : 0] s_axi_arid
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.s_axi_araddr(s_axi_araddr), // input [31 : 0] s_axi_araddr
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.s_axi_arlen(s_axi_arlen), // input [7 : 0] s_axi_arlen
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.s_axi_arsize(s_axi_arsize), // input [2 : 0] s_axi_arsize
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.s_axi_arburst(s_axi_arburst), // input [1 : 0] s_axi_arburst
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.s_axi_arvalid(s_axi_arvalid), // input s_axi_arvalid
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.s_axi_arready(s_axi_arready), // output s_axi_arready
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.s_axi_rid(s_axi_rid), // output [0 : 0] s_axi_rid
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.s_axi_rdata(s_axi_rdata), // output [63 : 0] s_axi_rdata
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.s_axi_rresp(s_axi_rresp), // output [1 : 0] s_axi_rresp
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.s_axi_rlast(s_axi_rlast), // output s_axi_rlast
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.s_axi_rvalid(s_axi_rvalid), // output s_axi_rvalid
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.s_axi_rready(s_axi_rready) // input s_axi_rready
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file axi4_bram_1kx64.v when simulating
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// the core, axi4_bram_1kx64. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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