233 lines
6.9 KiB
Verilog
233 lines
6.9 KiB
Verilog
/*******************************************************************************
|
|
* This file is owned and controlled by Xilinx and must be used solely *
|
|
* for design, simulation, implementation and creation of design files *
|
|
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
|
* devices or technologies is expressly prohibited and immediately *
|
|
* terminates your license. *
|
|
* *
|
|
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
|
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
|
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
|
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
|
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
|
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
|
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
|
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
|
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
|
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
|
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
|
* PARTICULAR PURPOSE. *
|
|
* *
|
|
* Xilinx products are not intended for use in life support appliances, *
|
|
* devices, or systems. Use in such applications are expressly *
|
|
* prohibited. *
|
|
* *
|
|
* (c) Copyright 1995-2013 Xilinx, Inc. *
|
|
* All rights reserved. *
|
|
*******************************************************************************/
|
|
// You must compile the wrapper file axi4_bram_1kx64.v when simulating
|
|
// the core, axi4_bram_1kx64. When compiling the wrapper file, be sure to
|
|
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
|
// instructions, please refer to the "CORE Generator Help".
|
|
|
|
// The synthesis directives "translate_off/translate_on" specified below are
|
|
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
|
// tools. Ensure they are correct for your synthesis tool(s).
|
|
|
|
`timescale 1ns/1ps
|
|
|
|
module axi4_bram_1kx64(
|
|
s_aclk,
|
|
s_aresetn,
|
|
s_axi_awid,
|
|
s_axi_awaddr,
|
|
s_axi_awlen,
|
|
s_axi_awsize,
|
|
s_axi_awburst,
|
|
s_axi_awvalid,
|
|
s_axi_awready,
|
|
s_axi_wdata,
|
|
s_axi_wstrb,
|
|
s_axi_wlast,
|
|
s_axi_wvalid,
|
|
s_axi_wready,
|
|
s_axi_bid,
|
|
s_axi_bresp,
|
|
s_axi_bvalid,
|
|
s_axi_bready,
|
|
s_axi_arid,
|
|
s_axi_araddr,
|
|
s_axi_arlen,
|
|
s_axi_arsize,
|
|
s_axi_arburst,
|
|
s_axi_arvalid,
|
|
s_axi_arready,
|
|
s_axi_rid,
|
|
s_axi_rdata,
|
|
s_axi_rresp,
|
|
s_axi_rlast,
|
|
s_axi_rvalid,
|
|
s_axi_rready
|
|
);
|
|
|
|
input s_aclk;
|
|
input s_aresetn;
|
|
input [0 : 0] s_axi_awid;
|
|
input [31 : 0] s_axi_awaddr;
|
|
input [7 : 0] s_axi_awlen;
|
|
input [2 : 0] s_axi_awsize;
|
|
input [1 : 0] s_axi_awburst;
|
|
input s_axi_awvalid;
|
|
output s_axi_awready;
|
|
input [63 : 0] s_axi_wdata;
|
|
input [7 : 0] s_axi_wstrb;
|
|
input s_axi_wlast;
|
|
input s_axi_wvalid;
|
|
output s_axi_wready;
|
|
output [0 : 0] s_axi_bid;
|
|
output [1 : 0] s_axi_bresp;
|
|
output s_axi_bvalid;
|
|
input s_axi_bready;
|
|
input [0 : 0] s_axi_arid;
|
|
input [31 : 0] s_axi_araddr;
|
|
input [7 : 0] s_axi_arlen;
|
|
input [2 : 0] s_axi_arsize;
|
|
input [1 : 0] s_axi_arburst;
|
|
input s_axi_arvalid;
|
|
output s_axi_arready;
|
|
output [0 : 0] s_axi_rid;
|
|
output [63 : 0] s_axi_rdata;
|
|
output [1 : 0] s_axi_rresp;
|
|
output s_axi_rlast;
|
|
output s_axi_rvalid;
|
|
input s_axi_rready;
|
|
|
|
// synthesis translate_off
|
|
|
|
BLK_MEM_GEN_V7_3 #(
|
|
.C_ADDRA_WIDTH(10),
|
|
.C_ADDRB_WIDTH(10),
|
|
.C_ALGORITHM(1),
|
|
.C_AXI_ID_WIDTH(1),
|
|
.C_AXI_SLAVE_TYPE(0),
|
|
.C_AXI_TYPE(1),
|
|
.C_BYTE_SIZE(8),
|
|
.C_COMMON_CLK(1),
|
|
.C_DEFAULT_DATA("0"),
|
|
.C_DISABLE_WARN_BHV_COLL(0),
|
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
|
.C_ENABLE_32BIT_ADDRESS(0),
|
|
.C_FAMILY("kintex7"),
|
|
.C_HAS_AXI_ID(1),
|
|
.C_HAS_ENA(1),
|
|
.C_HAS_ENB(1),
|
|
.C_HAS_INJECTERR(0),
|
|
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
|
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
|
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
|
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
|
.C_HAS_REGCEA(0),
|
|
.C_HAS_REGCEB(0),
|
|
.C_HAS_RSTA(0),
|
|
.C_HAS_RSTB(1),
|
|
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
|
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
|
.C_INIT_FILE("BlankString"),
|
|
.C_INIT_FILE_NAME("no_coe_file_loaded"),
|
|
.C_INITA_VAL("0"),
|
|
.C_INITB_VAL("0"),
|
|
.C_INTERFACE_TYPE(1),
|
|
.C_LOAD_INIT_FILE(0),
|
|
.C_MEM_TYPE(1),
|
|
.C_MUX_PIPELINE_STAGES(0),
|
|
.C_PRIM_TYPE(1),
|
|
.C_READ_DEPTH_A(1024),
|
|
.C_READ_DEPTH_B(1024),
|
|
.C_READ_WIDTH_A(64),
|
|
.C_READ_WIDTH_B(64),
|
|
.C_RST_PRIORITY_A("CE"),
|
|
.C_RST_PRIORITY_B("CE"),
|
|
.C_RST_TYPE("ASYNC"),
|
|
.C_RSTRAM_A(0),
|
|
.C_RSTRAM_B(0),
|
|
.C_SIM_COLLISION_CHECK("ALL"),
|
|
.C_USE_BRAM_BLOCK(0),
|
|
.C_USE_BYTE_WEA(1),
|
|
.C_USE_BYTE_WEB(1),
|
|
.C_USE_DEFAULT_DATA(0),
|
|
.C_USE_ECC(0),
|
|
.C_USE_SOFTECC(0),
|
|
.C_WEA_WIDTH(8),
|
|
.C_WEB_WIDTH(8),
|
|
.C_WRITE_DEPTH_A(1024),
|
|
.C_WRITE_DEPTH_B(1024),
|
|
.C_WRITE_MODE_A("READ_FIRST"),
|
|
.C_WRITE_MODE_B("READ_FIRST"),
|
|
.C_WRITE_WIDTH_A(64),
|
|
.C_WRITE_WIDTH_B(64),
|
|
.C_XDEVICEFAMILY("kintex7")
|
|
)
|
|
inst (
|
|
.S_ACLK(s_aclk),
|
|
.S_ARESETN(s_aresetn),
|
|
.S_AXI_AWID(s_axi_awid),
|
|
.S_AXI_AWADDR(s_axi_awaddr),
|
|
.S_AXI_AWLEN(s_axi_awlen),
|
|
.S_AXI_AWSIZE(s_axi_awsize),
|
|
.S_AXI_AWBURST(s_axi_awburst),
|
|
.S_AXI_AWVALID(s_axi_awvalid),
|
|
.S_AXI_AWREADY(s_axi_awready),
|
|
.S_AXI_WDATA(s_axi_wdata),
|
|
.S_AXI_WSTRB(s_axi_wstrb),
|
|
.S_AXI_WLAST(s_axi_wlast),
|
|
.S_AXI_WVALID(s_axi_wvalid),
|
|
.S_AXI_WREADY(s_axi_wready),
|
|
.S_AXI_BID(s_axi_bid),
|
|
.S_AXI_BRESP(s_axi_bresp),
|
|
.S_AXI_BVALID(s_axi_bvalid),
|
|
.S_AXI_BREADY(s_axi_bready),
|
|
.S_AXI_ARID(s_axi_arid),
|
|
.S_AXI_ARADDR(s_axi_araddr),
|
|
.S_AXI_ARLEN(s_axi_arlen),
|
|
.S_AXI_ARSIZE(s_axi_arsize),
|
|
.S_AXI_ARBURST(s_axi_arburst),
|
|
.S_AXI_ARVALID(s_axi_arvalid),
|
|
.S_AXI_ARREADY(s_axi_arready),
|
|
.S_AXI_RID(s_axi_rid),
|
|
.S_AXI_RDATA(s_axi_rdata),
|
|
.S_AXI_RRESP(s_axi_rresp),
|
|
.S_AXI_RLAST(s_axi_rlast),
|
|
.S_AXI_RVALID(s_axi_rvalid),
|
|
.S_AXI_RREADY(s_axi_rready),
|
|
.CLKA(),
|
|
.RSTA(),
|
|
.ENA(),
|
|
.REGCEA(),
|
|
.WEA(),
|
|
.ADDRA(),
|
|
.DINA(),
|
|
.DOUTA(),
|
|
.CLKB(),
|
|
.RSTB(),
|
|
.ENB(),
|
|
.REGCEB(),
|
|
.WEB(),
|
|
.ADDRB(),
|
|
.DINB(),
|
|
.DOUTB(),
|
|
.INJECTSBITERR(),
|
|
.INJECTDBITERR(),
|
|
.SBITERR(),
|
|
.DBITERR(),
|
|
.RDADDRECC(),
|
|
.S_AXI_INJECTSBITERR(),
|
|
.S_AXI_INJECTDBITERR(),
|
|
.S_AXI_SBITERR(),
|
|
.S_AXI_DBITERR(),
|
|
.S_AXI_RDADDRECC()
|
|
);
|
|
|
|
// synthesis translate_on
|
|
|
|
endmodule
|