102 lines
2.2 KiB
Verilog
102 lines
2.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module capture_ddrlvds
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#(parameter WIDTH=7,
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parameter B250=0)
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(input clk,
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input reset,
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input ssclk_p,
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input ssclk_n,
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input [WIDTH-1:0] in_p,
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input [WIDTH-1:0] in_n,
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output [(2*WIDTH)-1:0] out);
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wire [WIDTH-1:0] ddr_dat;
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wire ssclk;
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wire [(2*WIDTH)-1:0] out_pre1;
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wire ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr;
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IBUFGDS #(.DIFF_TERM("TRUE"))
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clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
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BUFMR clkbufmr (
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.I(ssclk),
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.O(ssclk_bufmr)
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);
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BUFIO clkbufio1 (
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.I(ssclk_bufmr),
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.O(ssclk_bufio1)
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);
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BUFIO clkbufio2 (
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.I(ssclk_bufmr),
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.O(ssclk_bufio2)
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);
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BUFR
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#(.SIM_DEVICE("7SERIES"),
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.BUFR_DIVIDE("BYPASS"))
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clkbufr (
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.I(ssclk_bufmr),
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.O(ssclk_bufr)
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);
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genvar i;
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generate
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for(i = 0; i < WIDTH; i = i + 1)
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begin : gen_lvds_pins
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if ((i == 10) && (B250 == 1)) begin
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IBUFDS #(.DIFF_TERM("FALSE")) ibufds
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(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
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IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr
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(.Q1(out_pre1[2*i]), .Q2(out_pre1[(2*i)+1]), .C(ssclk_bufio2),
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.CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
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end else begin
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IBUFDS #(.DIFF_TERM("TRUE")) ibufds
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(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
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IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr
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(.Q1(out_pre1[2*i]), .Q2(out_pre1[(2*i)+1]), .C(ssclk_bufio1),
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.CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
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end
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end
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endgenerate
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reg rd_en;
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wire full, empty, almost_empty;
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input_sample_fifo input_sample_fifo_i
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(
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.rst(reset), // input rst
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.wr_clk(ssclk_bufr), // input wr_clk
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.rd_clk(clk), // input rd_clk
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.din(out_pre1), // input [27 : 0] din
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.wr_en(1'b1), // input wr_en
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.rd_en(rd_en), // input rd_en
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.dout(out), // output [27 : 0] dout
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.full(full), // output full
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.empty(empty), // output empty
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.almost_empty(almost_empty) // output almost_empty
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);
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always @(posedge clk) begin
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if (reset)
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rd_en <= 0;
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else if (~almost_empty)
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rd_en <= 1;
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else if (empty)
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rd_en <= 0;
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end
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endmodule // capture_ddrlvds
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