164 lines
5.9 KiB
Verilog
Executable File
164 lines
5.9 KiB
Verilog
Executable File
// file: b200_clk_gen.v
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//
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// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//----------------------------------------------------------------------------
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// User entered comments
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//----------------------------------------------------------------------------
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// None
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//
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//----------------------------------------------------------------------------
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// "Output Output Phase Duty Pk-to-Pk Phase"
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// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
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//----------------------------------------------------------------------------
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// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
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// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
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// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
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//
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//----------------------------------------------------------------------------
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// "Input Clock Freq (MHz) Input Jitter (UI)"
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//----------------------------------------------------------------------------
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// __primary__________40.000____________0.010
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`timescale 1ps/1ps
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(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
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module b200_clk_gen
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(// Clock in ports
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input CLK_IN1_40_P,
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input CLK_IN1_40_N,
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// Clock out ports
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output CLK_OUT1_40_int,
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output CLK_OUT2_100_gpif,
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output CLK_OUT3_100_bus,
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// Status and control signals
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input RESET,
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output LOCKED
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);
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// Input buffering
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//------------------------------------
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IBUFGDS clkin1_buf
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(.O (clkin1),
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.I (CLK_IN1_40_P),
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.IB (CLK_IN1_40_N));
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// Clocking primitive
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//------------------------------------
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// Instantiation of the DCM primitive
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire psdone_unused;
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wire locked_int;
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wire [7:0] status_int;
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wire clkfb;
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wire clk0;
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wire clkfx;
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DCM_SP
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#(.CLKDV_DIVIDE (2.000),
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.CLKFX_DIVIDE (2),
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.CLKFX_MULTIPLY (5),
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.CLKIN_DIVIDE_BY_2 ("FALSE"),
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.CLKIN_PERIOD (25.0),
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.CLKOUT_PHASE_SHIFT ("NONE"),
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.CLK_FEEDBACK ("1X"),
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.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
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.PHASE_SHIFT (0),
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.STARTUP_WAIT ("FALSE"))
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dcm_sp_inst
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// Input clock
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(.CLKIN (clkin1),
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.CLKFB (clkfb),
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// Output clocks
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.CLK0 (clk0),
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.CLK90 (),
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.CLK180 (),
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.CLK270 (),
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.CLK2X (),
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.CLK2X180 (),
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.CLKFX (clkfx),
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.CLKFX180 (),
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.CLKDV (),
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// Ports for dynamic phase shift
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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// Other control and status signals
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.LOCKED (locked_int),
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.STATUS (status_int),
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.RST (RESET),
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// Unused pin- tie low
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.DSSEN (1'b0));
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assign LOCKED = locked_int;
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// Output buffering
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//-----------------------------------
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assign clkfb = CLK_OUT1_40_int;
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BUFG clkout1_buf
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(.O (CLK_OUT1_40_int),
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.I (clk0));
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BUFG clkout2_buf
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(.O (CLK_OUT2_100_gpif),
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.I (clkfx));
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BUFG clkout3_buf
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(.O (CLK_OUT3_100_bus),
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.I (clkfx));
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endmodule
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