Files
b210-k7-fpga/top/b200/coregen/b200_clk_gen.asy
T
Ben Hilburn c91b74de33 Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
2013-10-10 10:17:27 -07:00

34 lines
729 B
Plaintext

Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 b200_clk_gen
RECTANGLE Normal 32 32 576 1088
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk_in1_p
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName clk_in1_n
PINATTR Polarity IN
LINE Normal 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 608 80 576 80
PIN 608 80 RIGHT 36
PINATTR PinName clk_out1
PINATTR Polarity OUT
LINE Normal 608 176 576 176
PIN 608 176 RIGHT 36
PINATTR PinName clk_out2
PINATTR Polarity OUT
LINE Normal 608 272 576 272
PIN 608 272 RIGHT 36
PINATTR PinName clk_out3
PINATTR Polarity OUT
LINE Normal 608 976 576 976
PIN 608 976 RIGHT 36
PINATTR PinName locked
PINATTR Polarity OUT