114 lines
1.9 KiB
Verilog
114 lines
1.9 KiB
Verilog
reg [31:0] count_rx, count_tx;
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reg status;
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reg fail;
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//
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// Use task library
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//
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`define USE_TASKS
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initial
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begin
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clk <= 1'b0;
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reset <= 1'b0;
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clear <= 1'b0;
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i_tdata_r <= 0;
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i_tlast_r <= 0;
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i_tvalid_r <= 0;
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o_tready_r <= 0;
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end
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always
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#5 clk <= ~clk;
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initial
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begin
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count_tx = 2;
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count_rx = 2;
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status = 0;
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@(negedge clk);
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reset <= 1'b1;
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repeat(10) @(negedge clk);
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reset <= 1'b0;
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repeat(10) @(negedge clk);
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// Send 40 packets.
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repeat(40) begin
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send_raw_packet(count_tx);
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repeat(2) @(posedge clk);
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count_tx = count_tx + 1;
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@(posedge clk);
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end
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repeat(100) @(posedge clk);
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// Recieve 40 packets
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repeat(40) begin
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receive_raw_packet(count_rx,fail);
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status = status || fail;
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repeat(2) @(posedge clk);
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count_rx = count_rx + 1;
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@(posedge clk);
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end
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repeat(100) @(posedge clk);
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count_tx = 2;
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count_rx = 2;
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// Send 40 packets.
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repeat(40) begin
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send_raw_packet(count_tx);
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repeat(2) @(posedge clk);
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count_tx = count_tx + 1;
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@(posedge clk);
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end
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repeat(100) @(posedge clk);
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// Now fork so send and receive run concurrently
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fork
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begin
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// Send 40 packets.
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repeat(40) begin
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send_raw_packet(count_tx);
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repeat(2) @(posedge clk);
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count_tx = count_tx + 1;
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@(posedge clk);
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end
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end
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begin
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// Recieve 80 packets
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repeat(80) begin
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receive_raw_packet(count_rx,status);
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status = status || fail;
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repeat(2) @(posedge clk);
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count_rx = count_rx + 1;
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@(posedge clk);
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if (status !== 0) begin
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repeat(100) @(posedge clk);
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$display("FAILED.");
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$finish;
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end
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end
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end
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join
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// Now single threaded agian.
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repeat(100) @(posedge clk);
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$display;
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// Should not be able to get to here with FAIL status but check anyhow
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if (status != 0)
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$display("FAILED.");
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else
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$display("PASSED.");
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@(posedge clk);
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$finish;
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end
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//initial
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// o_tready = 1;
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