200 lines
7.3 KiB
Verilog
200 lines
7.3 KiB
Verilog
//////////////////////////////////////////////////////////////////////////////////
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// Copyright Ettus Research LLC
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// The ZYNQ FIFO configuration arbiter:
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// - holds configuration memory addresses
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// - setting and readback for slave state machines
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// - stream of memory addresses for master state machines
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//////////////////////////////////////////////////////////////////////////////////
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module zf_arbiter
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#(
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parameter STREAMS_WIDTH = 2,
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parameter CMDFIFO_DEPTH = 4,
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parameter PAGE_WIDTH = 16
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)
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(
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input clk,
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input rst,
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//------------------------------------------------------------------
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//-- settings interface
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//------------------------------------------------------------------
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input [31:0] set_addr,
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input [31:0] set_data,
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input set_stb,
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//------------------------------------------------------------------
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//-- readback interface
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//------------------------------------------------------------------
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input [31:0] rb_addr,
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output [31:0] rb_data,
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input rb_stb,
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//------------------------------------------------------------------
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//-- fifo interactive interface
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//------------------------------------------------------------------
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output [71:0] cmd_tdata,
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output cmd_tvalid,
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input cmd_tready,
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input [7:0] sts_tdata,
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input sts_tvalid,
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output sts_tready,
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//------------------------------------------------------------------
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//-- which stream to process? externally provided
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//------------------------------------------------------------------
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input [STREAMS_WIDTH-1:0] ext_stream,
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input stream_valid,
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output [31:0] debug
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);
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////////////////////////////////////////////////////////////////////////
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///////////////////////////// Begin R T L //////////////////////////////
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////////////////////////////////////////////////////////////////////////
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localparam NUM_STREAMS = (1 << STREAMS_WIDTH);
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reg [STREAMS_WIDTH-1:0] which_stream;
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//readback mux assignment
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reg [31:0] rb_data_i [NUM_STREAMS-1:0];
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assign rb_data = rb_data_i[rb_addr[STREAMS_WIDTH+4:5]];
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//cmd + sts fifo mux signals
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wire [72:0] cmd_data_i [NUM_STREAMS-1:0];
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assign cmd_tdata = cmd_data_i[which_stream];
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wire cmd_tvalid_i [NUM_STREAMS-1:0];
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wire sts_tready_i [NUM_STREAMS-1:0];
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////////////////////////////////////////////////////////////////////
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// state machine for driving fifo arbitration
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////////////////////////////////////////////////////////////////////
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localparam STATE_SET_WHICH_STREAM = 0;
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localparam STATE_ASSERT_DO_CMD = 1;
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localparam STATE_ASSERT_DO_STS = 2;
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localparam STATE_SOME_IDLE = 3;
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reg [1:0] state;
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always @(posedge clk) begin
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if (rst) begin
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state <= STATE_SET_WHICH_STREAM;
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which_stream <= 0;
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end
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else case (state)
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STATE_SET_WHICH_STREAM: begin
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if (cmd_tvalid_i[ext_stream]) state <= STATE_ASSERT_DO_CMD;
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which_stream <= ext_stream;
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end
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STATE_ASSERT_DO_CMD: begin
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if (cmd_tvalid && cmd_tready) state <= STATE_ASSERT_DO_STS;
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end
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STATE_ASSERT_DO_STS: begin
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if (sts_tvalid && sts_tready) state <= STATE_SOME_IDLE;
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end
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STATE_SOME_IDLE: begin
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state <= STATE_SET_WHICH_STREAM;
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end
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default: state <= STATE_SET_WHICH_STREAM;
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endcase //state
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end
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////////////////////////////////////////////////////////////////////
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// memory map + fifos for the host control/status
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////////////////////////////////////////////////////////////////////
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wire do_cmd = (state == STATE_ASSERT_DO_CMD);
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wire do_sts = (state == STATE_ASSERT_DO_STS);
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assign cmd_tvalid = do_cmd && cmd_tvalid_i[which_stream];
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assign sts_tready = do_sts && sts_tready_i[which_stream];
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genvar i;
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generate
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for (i=0; i < NUM_STREAMS; i=i+1) begin : stream_circuit
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wire [PAGE_WIDTH-3:0] set_addr32 = set_addr[PAGE_WIDTH-1:2];
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wire write_clear = set_stb && (set_addr32 == (0 + i*8));
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wire write_addr = set_stb && (set_addr32 == (1 + i*8));
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wire write_size = set_stb && (set_addr32 == (2 + i*8));
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wire write_sts_rdy = set_stb && (set_addr32 == (3 + i*8));
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wire write_sts = set_stb && (set_addr32 == (4 + i*8));
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wire [PAGE_WIDTH-3:0] rb_addr32 = rb_addr[PAGE_WIDTH-1:2];
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wire read_sig = (rb_addr32 == (0 + i*8));
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wire read_status = (rb_addr32 == (4 + i*8));
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wire read_sts_occupied = (rb_addr32 == (5 + i*8));
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wire read_cmd_addr_space = (rb_addr32 == (6 + i*8));
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wire read_cmd_size_space = (rb_addr32 == (7 + i*8));
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wire [15:0] sts_occupied, cmd_addr_space, cmd_size_space;
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wire [7:0] sts_readback;
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wire [15:0] this_stream = i;
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always @* begin
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if (read_sig) rb_data_i[i] <= {16'hACE0, this_stream};
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else if (read_status) rb_data_i[i] <= {24'b0, sts_readback};
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else if (read_sts_occupied) rb_data_i[i] <= {16'b0, sts_occupied};
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else if (read_cmd_addr_space) rb_data_i[i] <= {16'b0, cmd_addr_space};
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else if (read_cmd_size_space) rb_data_i[i] <= {16'b0, cmd_size_space};
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else rb_data_i[i] <= 32'h12345678;
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end
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wire [31:0] cmd_addr, cmd_size;
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wire cmd_addr_tvalid, cmd_size_tvalid;
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assign cmd_data_i[i][32+39:32+36] = 4'b0; //reserved - 0?
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assign cmd_data_i[i][32+35:64] = i[3:0]; //tag
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assign cmd_data_i[i][63:32] = cmd_addr;
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assign cmd_data_i[i][31] = 1'b0; //DRE ReAlignment Request
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assign cmd_data_i[i][30] = 1'b1; //always EOF for tlast stream
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assign cmd_data_i[i][29:24] = 6'b0; //DRE Stream Alignment
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assign cmd_data_i[i][23] = 1'b0; //reserved - 0?
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assign cmd_data_i[i][22:0] = cmd_size[22:0];
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axi_fifo #(.WIDTH(32), .SIZE(CMDFIFO_DEPTH)) crl_addr_fifo
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(
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.clk(clk), .reset(rst), .clear(write_clear),
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.i_tdata(set_data), .i_tvalid(write_addr), .i_tready(), .space(cmd_addr_space),
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.o_tdata(cmd_addr), .o_tvalid(cmd_addr_tvalid), .o_tready(cmd_tready && do_cmd && (which_stream == i)), .occupied()
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);
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axi_fifo #(.WIDTH(32), .SIZE(CMDFIFO_DEPTH)) crl_size_fifo
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(
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.clk(clk), .reset(rst), .clear(write_clear),
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.i_tdata(set_data), .i_tvalid(write_size), .i_tready(), .space(cmd_size_space),
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.o_tdata(cmd_size), .o_tvalid(cmd_size_tvalid), .o_tready(cmd_tready && do_cmd && (which_stream == i)), .occupied()
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);
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assign cmd_tvalid_i[i] = cmd_addr_tvalid && cmd_size_tvalid && stream_valid;
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wire dm_sts_tvalid = sts_tvalid && do_sts && (which_stream == i);
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axi_fifo #(.WIDTH(8), .SIZE(CMDFIFO_DEPTH)) sts_fifo
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(
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.clk(clk), .reset(rst), .clear(),
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.i_tdata((write_sts)?set_data[7:0]:sts_tdata), .i_tvalid(dm_sts_tvalid || write_sts), .i_tready(sts_tready_i[i]), .space(),
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.o_tdata(sts_readback), .o_tvalid(), .o_tready(write_sts_rdy), .occupied(sts_occupied)
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);
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end
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endgenerate
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assign debug[1:0] = state;
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assign debug[4] = cmd_tvalid;
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assign debug[5] = cmd_tready;
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assign debug[6] = sts_tvalid;
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assign debug[7] = sts_tready;
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assign debug[8] = ext_stream;
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assign debug[9] = which_stream;
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assign debug[15] = rb_addr[STREAMS_WIDTH+4:5];
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endmodule //zf_arbiter
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