179 lines
5.4 KiB
Verilog
179 lines
5.4 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "tx_enqueue.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module tx_enqueue(/*AUTOARG*/
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// Outputs
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pkt_tx_full, txdfifo_wdata, txdfifo_wstatus, txdfifo_wen,
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status_txdfifo_ovflow_tog,
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// Inputs
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clk_156m25, reset_156m25_n, pkt_tx_data, pkt_tx_val, pkt_tx_sop,
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pkt_tx_eop, pkt_tx_mod, txdfifo_wfull, txdfifo_walmost_full
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);
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`include "CRC32_D64.v"
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`include "CRC32_D8.v"
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`include "utils.v"
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input clk_156m25;
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input reset_156m25_n;
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input [63:0] pkt_tx_data;
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input pkt_tx_val;
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input pkt_tx_sop;
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input pkt_tx_eop;
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input [2:0] pkt_tx_mod;
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input txdfifo_wfull;
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input txdfifo_walmost_full;
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output pkt_tx_full;
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output [63:0] txdfifo_wdata;
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output [7:0] txdfifo_wstatus;
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output txdfifo_wen;
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output status_txdfifo_ovflow_tog;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg status_txdfifo_ovflow_tog;
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reg [63:0] txdfifo_wdata;
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reg txdfifo_wen;
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reg [7:0] txdfifo_wstatus;
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// End of automatics
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/*AUTOWIRE*/
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reg txd_ovflow;
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reg next_txd_ovflow;
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// Full status if data fifo is almost full.
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// Current packet can complete transfer since data input rate
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// matches output rate. But next packet must wait for more headroom.
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assign pkt_tx_full = txdfifo_walmost_full;
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always @(posedge clk_156m25 or negedge reset_156m25_n) begin
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if (reset_156m25_n == 1'b0) begin
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txd_ovflow <= 1'b0;
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status_txdfifo_ovflow_tog <= 1'b0;
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end
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else begin
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txd_ovflow <= next_txd_ovflow;
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//---
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// FIFO errors, used to generate interrupts
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if (next_txd_ovflow && !txd_ovflow) begin
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status_txdfifo_ovflow_tog <= ~status_txdfifo_ovflow_tog;
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end
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end
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end
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always @(/*AS*/pkt_tx_data or pkt_tx_eop or pkt_tx_mod or pkt_tx_sop
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or pkt_tx_val or txd_ovflow or txdfifo_wfull) begin
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txdfifo_wstatus = `TXSTATUS_NONE;
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txdfifo_wen = pkt_tx_val;
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next_txd_ovflow = txd_ovflow;
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`ifdef BIGENDIAN
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txdfifo_wdata = {pkt_tx_data[7:0], pkt_tx_data[15:8], pkt_tx_data[23:16], pkt_tx_data[31:24],
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pkt_tx_data[39:32], pkt_tx_data[47:40], pkt_tx_data[55:48],
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pkt_tx_data[63:56]};
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`else
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txdfifo_wdata = pkt_tx_data;
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`endif
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// Write SOP marker to fifo.
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if (pkt_tx_val && pkt_tx_sop) begin
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txdfifo_wstatus[`TXSTATUS_SOP] = 1'b1;
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end
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// Write EOP marker to fifo.
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if (pkt_tx_val) begin
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if (pkt_tx_eop) begin
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txdfifo_wstatus[2:0] = pkt_tx_mod;
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txdfifo_wstatus[`TXSTATUS_EOP] = 1'b1;
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end
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end
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// Overflow indication
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if (pkt_tx_val) begin
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if (txdfifo_wfull) begin
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next_txd_ovflow = 1'b1;
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end
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else if (pkt_tx_sop) begin
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next_txd_ovflow = 1'b0;
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end
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end
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end
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endmodule
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