106 lines
3.5 KiB
Verilog
106 lines
3.5 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "meta_sync_single.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module meta_sync_single(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, reset_n, in
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);
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parameter EDGE_DETECT = 0;
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input clk;
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input reset_n;
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input in;
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output out;
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reg out;
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generate
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if (EDGE_DETECT) begin
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reg meta;
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reg edg1;
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reg edg2;
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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meta <= 1'b0;
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edg1 <= 1'b0;
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edg2 <= 1'b0;
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out <= 1'b0;
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end
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else begin
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meta <= in;
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edg1 <= meta;
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edg2 <= edg1;
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out <= edg1 ^ edg2;
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end
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end
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end
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else begin
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reg meta;
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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meta <= 1'b0;
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out <= 1'b0;
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end
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else begin
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meta <= in;
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out <= meta;
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end
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end
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end
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endgenerate
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endmodule
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