155 lines
4.4 KiB
Verilog
155 lines
4.4 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "generic_mem_medium.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module generic_mem_xilinx_block(
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wclk,
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wrst_n,
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wen,
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waddr,
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wdata,
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rclk,
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rrst_n,
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ren,
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roen,
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raddr,
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rdata
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);
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//---
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// Parameters
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parameter DWIDTH = 32;
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parameter AWIDTH = 3;
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parameter RAM_DEPTH = (1 << AWIDTH);
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parameter SYNC_WRITE = 1;
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parameter SYNC_READ = 1;
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parameter REGISTER_READ = 0;
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//---
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// Ports
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input wclk;
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input wrst_n;
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input wen;
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input [AWIDTH:0] waddr;
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input [DWIDTH-1:0] wdata;
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input rclk;
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input rrst_n;
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input ren;
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input roen;
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input [AWIDTH:0] raddr;
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output [DWIDTH-1:0] rdata;
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// Registered outputs
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reg [DWIDTH-1:0] rdata;
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//---
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// Local declarations
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// Registers
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reg [DWIDTH-1:0] mem_rdata;
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// Memory - infer using Xilinx pragma for block ram.
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//synthesis attribute ram_style of mem is block
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reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
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// Variables
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integer i;
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//---
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// Memory Write
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// Generate synchronous write
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always @(posedge wclk)
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begin
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if (wen) begin
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mem[waddr[AWIDTH-1:0]] <= wdata;
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end
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end
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//---
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// Memory Read
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// Generate registered memory read
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always @(posedge rclk)
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begin
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if (!rrst_n) begin
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mem_rdata <= {(DWIDTH){1'b0}};
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end else if (ren) begin
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mem_rdata <= mem[raddr[AWIDTH-1:0]];
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end
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end
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generate
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if (REGISTER_READ) begin
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// Generate registered output
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always @(posedge rclk)
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begin
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if (!rrst_n) begin
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rdata <= {(DWIDTH){1'b0}};
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end else if (roen) begin
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rdata <= mem_rdata;
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end
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end
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end
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else begin
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// Generate unregisters output
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always @(mem_rdata)
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begin
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rdata = mem_rdata;
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end
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end
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endgenerate
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endmodule
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