66 lines
1.9 KiB
Verilog
66 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module simple_uart
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#(parameter CLKDIV_DEFAULT = 16'd0)
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(input clk_i, input rst_i,
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input we_i, input stb_i, input cyc_i, output reg ack_o,
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input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
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output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
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// Register Map
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localparam SUART_CLKDIV = 0;
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localparam SUART_TXLEVEL = 1;
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localparam SUART_RXLEVEL = 2;
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localparam SUART_TXCHAR = 3;
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localparam SUART_RXCHAR = 4;
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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reg [15:0] clkdiv;
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wire [7:0] rx_char;
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wire tx_fifo_full, rx_fifo_empty;
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wire [5:0] tx_fifo_level, rx_fifo_level;
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always @(posedge clk_i)
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if (rst_i)
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ack_o <= 1'b0;
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else
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ack_o <= wb_acc & ~ack_o;
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always @(posedge clk_i)
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if (rst_i)
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clkdiv <= CLKDIV_DEFAULT;
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else if (wb_wr)
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case(adr_i)
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SUART_CLKDIV : clkdiv <= dat_i[15:0];
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endcase // case(adr_i)
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always @(posedge clk_i)
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case (adr_i)
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SUART_TXLEVEL : dat_o <= tx_fifo_level;
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SUART_RXLEVEL : dat_o <= rx_fifo_level;
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SUART_RXCHAR : dat_o <= rx_char;
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endcase // case(adr_i)
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simple_uart_tx simple_uart_tx
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(.clk(clk_i),.rst(rst_i),
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.fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == SUART_TXCHAR)),
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.fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
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.clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
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simple_uart_rx simple_uart_rx
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(.clk(clk_i),.rst(rst_i),
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.fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == SUART_RXCHAR)),
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.fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty),
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.clkdiv(clkdiv),.rx(rx_i));
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assign tx_int_o = ~tx_fifo_full;
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assign rx_int_o = ~rx_fifo_empty;
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endmodule // simple_uart
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