93 lines
2.2 KiB
Verilog
93 lines
2.2 KiB
Verilog
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module new_tx_deframer
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(input clk, input reset, input clear,
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input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
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output [175:0] sample_tdata, output sample_tvalid, input sample_tready, output [31:0] debug);
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reg odd, send_at, eob;
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reg [11:0] seqnum;
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reg [31:0] sid;
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reg [63:0] send_time;
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wire [175:0] fifo_tdata = { odd, send_at, eob, i_tlast, seqnum/*12*/, sid, send_time/*64*/, i_tdata/*64*/ };
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wire fifo_tvalid, fifo_tready;
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reg [1:0] td_state;
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localparam TD_HEAD = 0;
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localparam TD_TIME = 1;
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localparam TD_BODY = 2;
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localparam TD_DUMP = 3;
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always @(posedge clk)
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if(reset | clear)
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begin
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td_state <= TD_HEAD;
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odd <= 1'b0;
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send_at <= 1'b0;
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eob <= 1'b0;
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seqnum <= 12'd0;
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sid <= 32'd0;
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send_time <= 64'h0;
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end // if (reset | clear)
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else
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case(td_state)
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TD_HEAD :
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if(i_tvalid)
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begin
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if(~i_tlast)
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if(i_tdata[63])
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td_state <= TD_DUMP;
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else if(i_tdata[61])
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td_state <= TD_TIME;
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else
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td_state <= TD_BODY;
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odd <= i_tdata[34];
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send_at <= i_tdata[61];
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eob <= i_tdata[60];
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seqnum <= i_tdata[59:48];
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sid <= i_tdata[31:0];
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// FIXME record trailer, length, and SID here
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end
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TD_TIME :
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if(i_tvalid)
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begin
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send_time <= i_tdata;
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if(~i_tlast)
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td_state <= TD_BODY;
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else
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td_state <= TD_HEAD;
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end
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TD_BODY :
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if(i_tvalid & fifo_tready)
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if(i_tlast)
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td_state <= TD_HEAD;
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TD_DUMP :
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if(i_tvalid)
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if(i_tlast)
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td_state <= TD_HEAD;
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endcase // case (td_state)
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assign fifo_tvalid = i_tvalid & (td_state == TD_BODY);
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assign i_tready = (td_state == TD_BODY) ? fifo_tready : 1'b1;
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axi_fifo_short #(.WIDTH(176)) ofifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(fifo_tdata), .i_tvalid(fifo_tvalid), .i_tready(fifo_tready),
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.o_tdata(sample_tdata), .o_tvalid(sample_tvalid), .o_tready(sample_tready),
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.space(), .occupied());
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assign debug = {
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sample_tvalid, // [8]
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sample_tready, // [7]
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i_tvalid, // [6]
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i_tready, // [5]
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td_state, // [4:3]
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odd, // [2]
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send_at, // [1]
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eob // [0]
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};
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endmodule // new_tx_deframer
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