187 lines
4.0 KiB
Verilog
187 lines
4.0 KiB
Verilog
module chdr_16sc_to_8sc
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#(parameter BASE=0)
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(input clk, input reset,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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//input side of device
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input [63:0] i_tdata,
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input i_tlast,
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input i_tvalid,
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output i_tready,
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//output side of device
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output reg [63:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready,
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output [31:0] debug
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);
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//pipeline register
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reg [63:0] hold_tdata;
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//bit assignments
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wire chdr_has_hdr = 1'b1;
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wire chdr_has_time = i_tdata[61];
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wire chdr_has_tlr = 1'b0;
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wire [7:0] rounded_i1;
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wire [7:0] rounded_q1;
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wire [7:0] rounded_i0;
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wire [7:0] rounded_q0;
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wire [7:0] rounded_i2;
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wire [7:0] rounded_q2;
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wire [7:0] rounded_i3;
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wire [7:0] rounded_q3;
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//chdr length calculations
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wire [15:0] chdr_header_lines8 = chdr_has_time? 16 : 8;
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wire [15:0] chdr_almost_payload_lines8 = ((i_tdata[47:32] - chdr_header_lines8) >> 1);
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wire [15:0] chdr_payload_lines8 = chdr_almost_payload_lines8 + chdr_header_lines8;
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wire [15:0] my_newhome;
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wire set_sid;
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setting_reg #(.my_addr(BASE), .width(17)) new_destination
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out({set_sid, my_newhome[15:0]}));
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localparam HEADER = 2'd0;//IDLE
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localparam TIME = 2'd1;
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localparam ODD = 2'd2;
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localparam EVEN = 2'd3;
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reg [1:0] state;
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always @(posedge clk) begin
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if (reset) begin
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state <= HEADER;
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hold_tdata <= 0;
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end
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else case(state)
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HEADER: begin
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if (i_tvalid && o_tready) begin
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state <= (i_tdata[61])? TIME : ODD;
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end
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end
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TIME: begin
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if (i_tvalid && o_tready) begin
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state <= (i_tlast)? HEADER: ODD;
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hold_tdata <= i_tdata;
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end
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end
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ODD: begin
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if (i_tvalid && o_tready) begin
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state <= (i_tlast)? HEADER: EVEN;
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hold_tdata <= i_tdata;
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end
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end
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EVEN: begin
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if (i_tvalid && o_tready)
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state <= (i_tlast) ? HEADER: ODD;
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hold_tdata <= i_tdata;
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end
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default: state <= HEADER;
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endcase
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end
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//assign 8 bit i and q signals from this line and last
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//new data processing
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round #(.bits_in(16),
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.bits_out(8))
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round_i2
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(.in(i_tdata[63:48]),
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.out(rounded_i2[7:0])
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);
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round #(.bits_in(16),
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.bits_out(8))
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round_q2
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(.in(i_tdata[47:32]),
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.out(rounded_q2[7:0])
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);
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round #(.bits_in(16),
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.bits_out(8))
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round_i3
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(.in(i_tdata[31:16]),
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.out(rounded_i3[7:0])
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);
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round #(.bits_in(16),
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.bits_out(8))
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round_q3
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(.in(i_tdata[15:0]),
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.out(rounded_q3[7:0])
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);
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// old data processing
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round #(.bits_in(16),
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.bits_out(8))
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round_i0(.in(hold_tdata[63:48]), .out(rounded_i0[7:0])
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);
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round #(.bits_in(16),
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.bits_out(8))
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round_q0
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(.in(hold_tdata[47:32]),
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.out(rounded_q0[7:0])
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);
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round #(.bits_in(16),
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.bits_out(8))
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round_i1
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(.in(hold_tdata[31:16]),
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.out(rounded_i1[7:0])
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);
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round #(.bits_in(16),
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.bits_out(8))
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round_q1
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(.in(hold_tdata[15:0]),
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.out(rounded_q1[7:0])
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);
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// main mux
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always @(*)
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case(state)
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HEADER: o_tdata = {i_tdata[63:48], chdr_payload_lines8,
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set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
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TIME: o_tdata = i_tdata;
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ODD: o_tdata = {rounded_i2, rounded_q2, rounded_i3, rounded_q3,rounded_i0, rounded_q0, rounded_i1, rounded_q1};
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EVEN: o_tdata = {rounded_i0, rounded_q0, rounded_i1, rounded_q1,rounded_i2, rounded_q2, rounded_i3, rounded_q3};
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default : o_tdata = i_tdata;
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endcase
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assign o_tvalid = i_tvalid && (state != ODD || i_tlast);
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assign i_tready = o_tready || (state == ODD && !i_tlast);
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assign o_tlast = i_tlast;
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endmodule
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