96 lines
2.4 KiB
Verilog
96 lines
2.4 KiB
Verilog
`timescale 1ns/1ps
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module ll8_to_axi64_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("ll8_to_axi64_tb.vcd");
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initial $dumpvars(0,ll8_to_axi64_tb);
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initial
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begin
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#1000 reset = 0;
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#2000000;
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$finish;
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end
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wire [63:0] tdata, tdata_int;
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wire [3:0] tuser, tuser_int;
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wire tlast, tlast_int;
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wire tvalid, tvalid_int, tready, tready_int;
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reg [7:0] ll_data;
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reg ll_eof, ll_error, ll_src_rdy;
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wire ll_dst_rdy;
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wire [7:0] ll_data2;
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wire ll_eof2, ll_src_rdy2, ll_dst_rdy2;
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localparam RPT_COUNT = 12;
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initial
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begin
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ll_src_rdy <= 0;
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while(reset)
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@(posedge clk);
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@(posedge clk);
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{ll_error, ll_eof, ll_data} <= { 1'b0, 1'b0, 8'hA0 };
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repeat(RPT_COUNT-1)
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begin
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ll_src_rdy <= 1;
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@(posedge clk);
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ll_data <= ll_data + 1;
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end
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ll_eof <= 1;
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ll_data <= ll_data + 1;
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@(posedge clk);
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{ll_error, ll_eof, ll_data} <= { 1'b0, 1'b0, 8'hC0 };
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repeat(RPT_COUNT-1)
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begin
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ll_src_rdy <= 1;
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@(posedge clk);
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ll_data <= ll_data + 1;
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end
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ll_eof <= 1; ll_error <= 1;
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ll_data <= ll_data + 1;
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@(posedge clk);
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ll_src_rdy <= 1'b0;
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end
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ll8_to_axi64 #(.START_BYTE(6), .LABEL(8'h89)) ll8_to_axi64
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(.clk(clk), .reset(reset), .clear(1'b0),
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.ll_data(ll_data), .ll_eof(ll_eof), .ll_error(ll_error), .ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy),
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.axi64_tdata(tdata), .axi64_tlast(tlast), .axi64_tuser(tuser), .axi64_tvalid(tvalid), .axi64_tready(tready) );
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axi_fifo_short #(.WIDTH(69)) axi_fifo_short
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({tlast,tuser,tdata}), .i_tvalid(tvalid), .i_tready(tready),
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.o_tdata({tlast_int,tuser_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int));
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axi64_to_ll8 #(.START_BYTE(6)) axi64_to_ll8
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(.clk(clk), .reset(reset), .clear(1'b0),
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.axi64_tdata(tdata_int), .axi64_tlast(tlast_int), .axi64_tuser(tuser_int), .axi64_tvalid(tvalid_int), .axi64_tready(tready_int),
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.ll_data(ll_data2), .ll_eof(ll_eof2), .ll_src_rdy(ll_src_rdy2), .ll_dst_rdy(ll_dst_rdy2) );
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/*
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always @(posedge clk)
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if(ll_src_rdy2 & ll_dst_rdy2)
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$display("EOF %x\tDATA %x",ll_eof2, ll_data2);
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*/
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assign ll_dst_rdy2 = 1;
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always @(posedge clk)
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if(tvalid_int & tready_int)
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$display("TERR %x\tTUSER %x\tTLAST %x\tTDATA %x",tuser_int[3],tuser_int[2:0], tlast_int, tdata_int);
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endmodule // ll8_to_axi64_tb
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