32 lines
964 B
Verilog
32 lines
964 B
Verilog
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module axi_fifo64_to_fifo32
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(input clk, input reset, input clear,
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input [63:0] i_tdata, input [2:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
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output [31:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
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);
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wire short_last = i_tlast & ((i_tuser == 3'd1) | (i_tuser == 3'd2) | (i_tuser == 3'd3) | (i_tuser == 3'd4));
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reg state;
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always @(posedge clk)
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if(reset | clear)
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state <= 1'b0;
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else
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if(i_tvalid & o_tready)
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case(state)
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1'b0 :
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if(~short_last)
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state <= 1'b1;
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1'b1 :
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state <= 1'b0;
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endcase // case (state)
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assign o_tdata = (state == 0) ? i_tdata[63:32] : i_tdata[31:0];
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assign o_tuser = o_tlast ? i_tuser[1:0] : 2'd0;
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assign o_tlast = i_tlast & ((state == 1'b1) | short_last);
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assign o_tvalid = i_tvalid;
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assign i_tready = o_tready & ((state == 1'b1) | short_last);
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endmodule // axi_fifo64_to_fifo32
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