24 lines
423 B
Verilog
24 lines
423 B
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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//
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// Sign extension "macro"
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// bits_out should be greater than bits_in
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module sign_extend (in,out);
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parameter bits_in=0; // FIXME Quartus insists on a default
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parameter bits_out=0;
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input [bits_in-1:0] in;
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output [bits_out-1:0] out;
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assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
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endmodule
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