59 lines
1.4 KiB
Verilog
59 lines
1.4 KiB
Verilog
`timescale 1ns/1ps
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module ddc_chain_x300_tb();
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`ifdef ISIM
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`else //iverilog implied.
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// xlnx_glbl glbl (.GSR(),.GTS());
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`endif
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localparam SR_TX_DSP = 8;
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("ddc_chain_x300_tb.vcd");
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initial $dumpvars(0,ddc_chain_x300_tb);
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reg run = 0;
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wire strobe;
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initial
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begin
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#1000 reset = 0;
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@(posedge clk);
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set_addr <= 0; set_data <= 32'd8434349; set_stb <= 1; @(posedge clk); // CORDIC
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set_addr <= 1; set_data <= 18'd19800; set_stb <= 1; @(posedge clk); // Scale factor
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set_addr <= 2; set_data <= 10'h003; set_stb <= 1; @(posedge clk); // Decim control
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set_addr <= 3; set_data <= 0; set_stb <= 1; @(posedge clk); // Swap iq
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set_addr <= 4; set_data <= 0; set_stb <= 1; @(posedge clk); // filter taps
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set_stb <= 0;
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repeat(10)
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@(posedge clk);
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run <= 1'b1;
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#30000;
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$finish;
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end
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reg [7:0] set_addr;
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reg [31:0] set_data;
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reg set_stb = 1'b0;
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wire [15:0] i_out, q_out;
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wire [23:0] rx_fe_i, rx_fe_q;
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assign rx_fe_i = 24'd8388607;
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assign rx_fe_q = 24'd8388607;
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//assign rx_fe_q = 0;
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ddc_chain_x300 #(.BASE(0), .DSPNO(0), .WIDTH(24)) ddc_chain
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(.clk(clk), .rst(reset), .clr(1'b0),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
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.sample({i_out,q_out}), .run(run), .strobe(strobe),
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.debug() );
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endmodule // new_tx_tb
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