422 lines
14 KiB
Verilog
422 lines
14 KiB
Verilog
module axi_dram_fifo_tb;
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reg clk; // Global AXI clock
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reg reset; // Global reset, active high.
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reg clear;
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wire aresetn; // Global AXI reset, active low.
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//
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// AXI Write address channel
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//
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wire [0 : 0] axi_awid; // Write address ID. This signal is the identification tag for the write address signals
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wire [31 : 0] axi_awaddr; // Write address. The write address gives the address of the first transfer in a write burst
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wire [7 : 0] axi_awlen; // Burst length. The burst length gives the exact number of transfers in a burst.
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wire [2 : 0] axi_awsize; // Burst size. This signal indicates the size of each transfer in the burst.
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wire [1 : 0] axi_awburst; // Burst type. The burst type and the size information, determine how the address is calculated
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wire [0 : 0] axi_awlock; // Lock type. Provides additional information about the atomic characteristics of the transfer.
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wire [3 : 0] axi_awcache; // Memory type. This signal indicates how transactions are required to progress
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wire [2 : 0] axi_awprot; // Protection type. This signal indicates the privilege and security level of the transaction
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wire [3 : 0] axi_awqos; // Quality of Service, QoS. The QoS identifier sent for each write transaction
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wire [3 : 0] axi_awregion; // Region identifier. Permits a single physical interface on a slave to be re-used.
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wire [0 : 0] axi_awuser; // User signal. Optional User-defined signal in the write address channel.
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wire axi_awvalid; // Write address valid. This signal indicates that the channel is signaling valid write addr
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wire axi_awready; // Write address ready. This signal indicates that the slave is ready to accept an address
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//
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// AXI Write data channel.
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//
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wire [63 : 0] axi_wdata; // Write data
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wire [7 : 0] axi_wstrb; // Write strobes. This signal indicates which byte lanes hold valid data.
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wire axi_wlast; // Write last. This signal indicates the last transfer in a write burst
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wire [0 : 0] axi_wuser; // User signal. Optional User-defined signal in the write data channel.
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wire axi_wvalid; // Write valid. This signal indicates that valid write data and strobes are available.
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wire axi_wready; // Write ready. This signal indicates that the slave can accept the write data.
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//
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// AXI Write response channel signals
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//
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wire [0 : 0] axi_bid; // Response ID tag. This signal is the ID tag of the write response.
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wire [1 : 0] axi_bresp; // Write response. This signal indicates the status of the write transaction.
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wire [0 : 0] axi_buser; // User signal. Optional User-defined signal in the write response channel.
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wire axi_bvalid; // Write response valid. This signal indicates that the channel is signaling a valid response
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wire axi_bready; // Response ready. This signal indicates that the master can accept a write response
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//
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// AXI Read address channel
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//
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wire [0 : 0] axi_arid; // Read address ID. This signal is the identification tag for the read address group of signals
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wire [31 : 0] axi_araddr; // Read address. The read address gives the address of the first transfer in a read burst
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wire [7 : 0] axi_arlen; // Burst length. This signal indicates the exact number of transfers in a burst.
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wire [2 : 0] axi_arsize; // Burst size. This signal indicates the size of each transfer in the burst.
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wire [1 : 0] axi_arburst; // Burst type. The burst type and the size information determine how the address for each transfer
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wire [0 : 0] axi_arlock; // Lock type. This signal provides additional information about the atomic characteristics
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wire [3 : 0] axi_arcache; // Memory type. This signal indicates how transactions are required to progress
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wire [2 : 0] axi_arprot; // Protection type. This signal indicates the privilege and security level of the transaction
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wire [3 : 0] axi_arqos; // Quality of Service, QoS. QoS identifier sent for each read transaction.
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wire [3 : 0] axi_arregion; // Region identifier. Permits a single physical interface on a slave to be re-used
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wire [0 : 0] axi_aruser; // User signal. Optional User-defined signal in the read address channel.
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wire axi_arvalid; // Read address valid. This signal indicates that the channel is signaling valid read addr
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wire axi_arready; // Read address ready. This signal indicates that the slave is ready to accept an address
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//
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// AXI Read data channel
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//
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wire [0 : 0] axi_rid; // Read ID tag. This signal is the identification tag for the read data group of signals
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wire [63 : 0] axi_rdata; // Read data.
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wire [1 : 0] axi_rresp; // Read response. This signal indicates the status of the read transfer
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wire axi_rlast; // Read last. This signal indicates the last transfer in a read burst.
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wire [0 : 0] axi_ruser; // User signal. Optional User-defined signal in the read data channel.
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wire axi_rvalid; // Read valid. This signal indicates that the channel is signaling the required read data.
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wire axi_rready; // Read ready. This signal indicates that the master can accept the read data and response
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//
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// CHDR friendly AXI stream input
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//
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wire [63:0] i_tdata;
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wire i_tlast;
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wire i_tvalid;
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wire i_tready;
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//
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// CHDR friendly AXI Stream output
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//
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wire [63:0] o_tdata;
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wire o_tlast;
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wire o_tvalid;
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wire o_tready;
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//
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// These registers optionaly used
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// to drive nets through procedural assignments in test bench.
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// These drivers default to tri-stated.
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//
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reg [63:0] i_tdata_r;
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reg i_tlast_r;
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reg i_tvalid_r;
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reg o_tready_r;
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assign i_tdata = i_tdata_r;
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assign i_tlast = i_tlast_r;
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assign i_tvalid = i_tvalid_r;
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assign o_tready = o_tready_r;
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initial
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begin
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i_tdata_r <= 64'hzzzz_zzzz_zzzz_zzzz;
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i_tlast_r <= 1'bz;
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i_tvalid_r <= 1'bz;
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o_tready_r <= 1'bz;
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end
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axi_dram_fifo
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#(.SIZE(13))
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axi_dram_fifo_i1
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(
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.bus_clk(clk), // input s_aclk
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.bus_reset(reset), // input s_aresetn
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.clear(clear),
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.dram_clk(clk), // input s_aclk
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.dram_reset(reset), // input s_aresetn
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// Write control
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.m_axi_awid(axi_awid), // input [0 : 0] s_axi_awid
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.m_axi_awaddr(axi_awaddr), // input [31 : 0] s_axi_awaddr
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.m_axi_awlen(axi_awlen), // input [7 : 0] s_axi_awlen
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.m_axi_awsize(axi_awsize), // input [2 : 0] s_axi_awsize
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.m_axi_awburst(axi_awburst), // input [1 : 0] s_axi_awburst
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.m_axi_awvalid(axi_awvalid), // input s_axi_awvalid
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.m_axi_awready(axi_awready), // output s_axi_awready
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.m_axi_awlock(),
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.m_axi_awcache(),
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.m_axi_awprot(),
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.m_axi_awqos(),
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.m_axi_awregion(),
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.m_axi_awuser(),
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// Write Data
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.m_axi_wdata(axi_wdata), // input [63 : 0] s_axi_wdata
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.m_axi_wstrb(axi_wstrb), // input [7 : 0] s_axi_wstrb
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.m_axi_wlast(axi_wlast), // input s_axi_wlast
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.m_axi_wvalid(axi_wvalid), // input s_axi_wvalid
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.m_axi_wready(axi_wready), // output s_axi_wready
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.m_axi_wuser(),
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// Write Response
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.m_axi_bid(axi_bid), // output [0 : 0] s_axi_bid
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.m_axi_bresp(axi_bresp), // output [1 : 0] s_axi_bresp
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.m_axi_bvalid(axi_bvalid), // output s_axi_bvalid
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.m_axi_bready(axi_bready), // input s_axi_bready
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.m_axi_buser(),
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// Read Control
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.m_axi_arid(axi_arid), // input [0 : 0] s_axi_arid
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.m_axi_araddr(axi_araddr), // input [31 : 0] s_axi_araddr
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.m_axi_arlen(axi_arlen), // input [7 : 0] s_axi_arlen
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.m_axi_arsize(axi_arsize), // input [2 : 0] s_axi_arsize
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.m_axi_arburst(axi_arburst), // input [1 : 0] s_axi_arburst
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.m_axi_arvalid(axi_arvalid), // input s_axi_arvalid
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.m_axi_arready(axi_arready), // output s_axi_arready
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.m_axi_arlock(),
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.m_axi_arcache(),
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.m_axi_arprot(),
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.m_axi_arqos(),
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.m_axi_arregion(),
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.m_axi_aruser(),
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// Read Data
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.m_axi_rid(axi_rid), // output [0 : 0] s_axi_rid
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.m_axi_rdata(axi_rdata), // output [63 : 0] s_axi_rdata
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.m_axi_rresp(axi_rresp), // output [1 : 0] s_axi_rresp
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.m_axi_rlast(axi_rlast), // output s_axi_rlast
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.m_axi_rvalid(axi_rvalid), // output s_axi_rvalid
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.m_axi_rready(axi_rready), // input s_axi_rready
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.m_axi_ruser(),
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// CHDR in
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.i_tdata(i_tdata),
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.i_tlast(i_tlast),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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// CHDR out
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.o_tdata(o_tdata),
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.o_tlast(o_tlast),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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//
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.supress_threshold(16'h0),
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.supress_enable(1'b0)
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);
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axi4_bram_1kx64 axi4_bram_1kx64_i1
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(
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.s_aclk(clk), // input s_aclk
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.s_aresetn(aresetn), // input s_aresetn
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.s_axi_awid(axi_awid), // input [0 : 0] s_axi_awid
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.s_axi_awaddr(axi_awaddr), // input [31 : 0] s_axi_awaddr
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.s_axi_awlen(axi_awlen), // input [7 : 0] s_axi_awlen
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.s_axi_awsize(axi_awsize), // input [2 : 0] s_axi_awsize
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.s_axi_awburst(axi_awburst), // input [1 : 0] s_axi_awburst
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.s_axi_awvalid(axi_awvalid), // input s_axi_awvalid
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.s_axi_awready(axi_awready), // output s_axi_awready
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.s_axi_wdata(axi_wdata), // input [63 : 0] s_axi_wdata
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.s_axi_wstrb(axi_wstrb), // input [7 : 0] s_axi_wstrb
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.s_axi_wlast(axi_wlast), // input s_axi_wlast
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.s_axi_wvalid(axi_wvalid), // input s_axi_wvalid
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.s_axi_wready(axi_wready), // output s_axi_wready
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.s_axi_bid(axi_bid), // output [0 : 0] s_axi_bid
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.s_axi_bresp(axi_bresp), // output [1 : 0] s_axi_bresp
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.s_axi_bvalid(axi_bvalid), // output s_axi_bvalid
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.s_axi_bready(axi_bready), // input s_axi_bready
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.s_axi_arid(axi_arid), // input [0 : 0] s_axi_arid
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.s_axi_araddr(axi_araddr), // input [31 : 0] s_axi_araddr
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.s_axi_arlen(axi_arlen), // input [7 : 0] s_axi_arlen
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.s_axi_arsize(axi_arsize), // input [2 : 0] s_axi_arsize
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.s_axi_arburst(axi_arburst), // input [1 : 0] s_axi_arburst
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.s_axi_arvalid(axi_arvalid), // input s_axi_arvalid
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.s_axi_arready(axi_arready), // output s_axi_arready
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.s_axi_rid(axi_rid), // output [0 : 0] s_axi_rid
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.s_axi_rdata(axi_rdata), // output [63 : 0] s_axi_rdata
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.s_axi_rresp(axi_rresp), // output [1 : 0] s_axi_rresp
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.s_axi_rlast(axi_rlast), // output s_axi_rlast
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.s_axi_rvalid(axi_rvalid), // output s_axi_rvalid
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.s_axi_rready(axi_rready) // input s_axi_rready
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);
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//
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//
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//
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task send_ramp;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] sid;
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reg [31:0] data;
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reg [11:0] seqno;
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begin
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seqno = 0;
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data = 0;
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send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
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seqno = seqno + 1;
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data <= data + len;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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send_packet(len, data, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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data <= data + len;
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end
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if(burst_count > 1)
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send_packet(len, data, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_ramp
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task send_dc;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] sid;
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reg [31:0] data;
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reg [11:0] seqno;
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begin
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seqno = 0;
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data = 1 << 14;
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send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
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seqno = seqno + 1;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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send_packet(len, data, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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end
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if(burst_count > 1)
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send_packet(len, data, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_ramp
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task send_burst;
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input [31:0] burst_count;
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input [31:0] len;
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input [31:0] start_data;
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input [63:0] send_time;
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input [11:0] start_seqnum;
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input send_at;
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input [31:0] sid;
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reg [11:0] seqno;
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begin
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seqno = start_seqnum;
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send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
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seqno = seqno + 1;
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if(burst_count > 2)
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repeat (burst_count - 2)
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begin
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send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
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seqno = seqno + 1;
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end
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if(burst_count > 1)
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send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
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end
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endtask // send_burst
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task send_packet;
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input [31:0] len;
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input [31:0] start_data;
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input [63:0] send_time;
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input [11:0] pkt_seqnum;
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input eob;
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input send_at;
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input [31:0] sid;
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reg [31:0] samp0, samp1;
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begin
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// Send a packet
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samp0 <= start_data;
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samp1 <= start_data + 1;
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@(posedge clk);
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i_tlast_r <= 0;
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i_tdata_r <= { 1'b0, 1'b0 /*trl*/, send_at, eob, pkt_seqnum, len[15:0]+16'd2+send_at+send_at, sid };
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i_tvalid_r <= 1;
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@(posedge clk)
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if(send_at)
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begin
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i_tdata_r <= send_time;
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@(posedge clk);
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end
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repeat (len[31:1]+len[0]-1)
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begin
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i_tdata_r <= {samp0,samp1};
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samp0 <= samp0 + 2;
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samp1 <= samp1 + 2;
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@(posedge clk);
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end
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i_tdata_r <= {samp0,samp1};
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i_tlast_r <= 1'b1;
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@(posedge clk);
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i_tvalid_r <= 0;
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@(posedge clk);
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end
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endtask // send_packet
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task send_raw_packet;
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input [31:0] len;
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reg [63:0] data;
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begin
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data = 0;
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@(posedge clk);
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repeat (len-1) begin
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i_tlast_r <= 0;
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i_tdata_r <= data;
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i_tvalid_r <= 1;
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@(posedge clk);
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while (~i_tready) @(posedge clk);
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data = data + 1;
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end
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i_tlast_r <= 1;
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i_tdata_r <= data;
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i_tvalid_r <= 1;
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@(posedge clk);
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while (~i_tready) @(posedge clk);
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i_tvalid_r <= 0;
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@(posedge clk);
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end
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endtask // send_raw_packet
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task receive_raw_packet;
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input [31:0] len;
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output fail;
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reg [63:0] data;
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begin
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data = 0;
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fail = 0;
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@(posedge clk);
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repeat (len-1) begin
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o_tready_r <= 1;
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@(posedge clk);
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while (~o_tvalid) @(posedge clk);
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//$display("Data = %d, o_tdata = %d, o_tlast = %d",data,o_tdata,o_tlast);
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fail = fail || (data !== o_tdata);
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fail = fail || ~(o_tlast === 0);
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data = data + 1;
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end
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o_tready_r <= 1;
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@(posedge clk);
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while (~o_tvalid) @(posedge clk);
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//$display("Data = %d, o_tdata = %d, o_tlast = %d",data,o_tdata,o_tlast);
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fail = fail || (data !== o_tdata);
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fail = fail || ~(o_tlast === 1);
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o_tready_r <= 0;
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@(posedge clk);
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if (fail) $display("receive_raw_packet size %d failed",len);
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end
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endtask // receive_raw_packet
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assign aresetn = ~reset;
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//
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// Bring in a simulation script here
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//
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`include "simulation_script.v"
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endmodule // axi_dram_fifo_tb
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