35 lines
1.1 KiB
Makefile
35 lines
1.1 KiB
Makefile
#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one top-level module
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SIM_TOP = axis_load_split_merge_all_tb
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# Add test bench, user design under test, and
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# additional user created files
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SIM_SRCS = $(abspath \
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axis_load_split_merge_tb.sv \
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axis_load_split_merge_all_tb.sv \
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)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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