428 lines
14 KiB
Systemverilog
428 lines
14 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_100g_lbus2axis
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//
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// Description:
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// Translate from lbus (xilinx segmented ifc) to
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// AXI4S.
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//
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// Built using example provided from Xilinx
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//
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// Notes on timing difficulty
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// The path back to pop is challenged
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// -LBUS is popped out of the AXI flop
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// -LBUS is rotated N to 1 Mux (N= number of segments) For 100g N=4
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// -Find where EOP is (search for the first 1)
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// -Unrotate the number of words and use that to calculate pop
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// -pop is used to update the AXI flop registers
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//
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// Fifo Output
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// Data starts from the AXI flop
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// Invalid control is forced to zero (necessary for algorithm)
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// It's not necessary to force all the data to zero just the control plane.
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//
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// Fifo output data is rotated (4 to 1) mux then reinterpreted as lbus data
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//
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// The rotated control signals are analyzed to determine
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// no_eop, no_sop, some_empty, no_ena
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//
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// eop is specifically inspected in a 4in,4out function to find a pseudo
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// one hot. this is unrotated along with enable, and combined with
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// datavalid to determine the next pop.
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//
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module eth_100g_lbus2axis
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import PkgEth100gLbus::*;
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(
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// AXIS IF
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AxiStreamIf.master axis,
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// Lbus Segments
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input lbus_t lbus_in [NUM_SEG-1:0]
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);
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localparam SEG_BYTES = SEG_DATA_WIDTH/8;
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localparam SEG_MTY_WIDTH = $clog2(SEG_BYTES);
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localparam SEG_SHMEAR_WIDTH = SEG_DATA_WIDTH + SEG_MTY_WIDTH + 4;
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// Data Input to FIFO ///////////
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//////////////////////////////////////////////////////////////////////////////////
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lbus_t lbus_fout_p[NUM_SEG-1:0]; //{ena,err,eop,sop,mty,data}
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lbus_t lbus_fout[NUM_SEG-1:0]; //{ena,err,eop,sop,mty,data}
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//FIFO Logic
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logic push;
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logic [NUM_SEG-1:0] pop;
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logic [NUM_SEG-1:0] empty;
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// always push the fifo on all lanes
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assign push = lbus_in[0].ena;
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// For each lane of incoming data place it into a separate FIFO
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generate
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begin : gen_seg_fifo
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for(genvar gseg1 = 0; gseg1 < NUM_SEG; gseg1=gseg1+1) begin
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//////////////////////////////////////////////////////////////////////////////////
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// INLINE FIFO
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//////////////////////////////////////////////////////////////////////////////////
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logic input_fifo_i_tready;
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logic input_fifo_o_tvalid;
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logic input_fifo_o_tready;
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logic input_flop_o_tvalid;
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lbus_t lbus_fifo;
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// simulation error if we push a full fifo
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// synopsys translate_off
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always_comb begin
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if (push) begin
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assert (input_fifo_i_tready) else $error("Pushing full fifo!");
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end
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end
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// synopsys translate_on
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// input FIFO used for storing data using SRLC32E primitives
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axi_fifo_short #(
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.WIDTH($bits(lbus_in[gseg1]))
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) input_fifo (
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.clk(axis.clk),
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.reset(axis.rst),
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.clear(1'b0),
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.i_tdata(lbus_in[gseg1]),
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.i_tvalid(push),
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.i_tready(input_fifo_i_tready),
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.o_tdata(lbus_fifo),
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.o_tvalid(input_fifo_o_tvalid),
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.o_tready(input_fifo_o_tready),
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.space(),
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.occupied()
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);
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// output flop attached to register to break critical timing paths
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axi_fifo_flop2 #(
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.WIDTH($bits(lbus_in[gseg1]))
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) critical_fifo_flop (
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.clk(axis.clk),
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.reset(axis.rst),
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.clear(1'b0),
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.i_tdata(lbus_fifo),
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.i_tvalid(input_fifo_o_tvalid),
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.i_tready(input_fifo_o_tready),
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.o_tdata(lbus_fout_p[gseg1]),
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.o_tvalid(input_flop_o_tvalid),
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.o_tready(pop[gseg1]),
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.space(),
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.occupied()
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);
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assign empty[gseg1] = ~input_flop_o_tvalid;
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// clear the enables if this fifo segment is not valid
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always_comb begin
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//default assignment
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lbus_fout[gseg1] = lbus_fout_p[gseg1];
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if (empty[gseg1]) begin
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// clear ena,err,eop,sop,mty (But not data - saves fanout!)
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lbus_fout[gseg1].ena = 0;
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lbus_fout[gseg1].err = 0;
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lbus_fout[gseg1].eop = 0;
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lbus_fout[gseg1].sop = 0;
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lbus_fout[gseg1].mty = '0;
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end else begin
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// clear bits if the segment isn't enabled
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lbus_fout[gseg1].eop = lbus_fout_p[gseg1].eop && lbus_fout_p[gseg1].ena;
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lbus_fout[gseg1].sop = lbus_fout_p[gseg1].sop && lbus_fout_p[gseg1].ena;
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lbus_fout[gseg1].err = lbus_fout_p[gseg1].err && lbus_fout_p[gseg1].ena;
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end
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end
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end
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end : gen_seg_fifo
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endgenerate
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// post rotation lbus signals
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lbus_t lbus_rot [NUM_SEG-1:0];
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// rotated signals as vectors for decision making
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logic [NUM_SEG-1:0] ena;
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logic [NUM_SEG-1:0] sop;
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logic [NUM_SEG-1:0] eop;
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logic [NUM_SEG-1:0] rot_ena;
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logic [NUM_SEG-1:0] rot_sop;
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logic [NUM_SEG-1:0] rot_eop;
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logic [NUM_SEG-1:0] rot_empty;
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always_comb begin
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foreach (rot_ena[s]) begin
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ena[s] = lbus_fout[s].ena;
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sop[s] = lbus_fout[s].sop;
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eop[s] = lbus_fout[s].eop;
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rot_ena[s] = lbus_rot[s].ena;
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rot_sop[s] = lbus_rot[s].sop;
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rot_eop[s] = lbus_rot[s].eop;
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end
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end
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logic [$clog2(NUM_SEG)-1:0] rot;
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// Generate Decision Information ///////////
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//////////////////////////////////////////////////////////////////////////////////
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logic no_sop;
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logic no_eop;
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logic no_ena;
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logic some_empty;
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logic send_idle;
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always_comb begin
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no_sop = sop == 0;
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no_eop = eop == 0;
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no_ena = ena == 0;
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// check for an empy byte
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some_empty = 1'b0;
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foreach (ena[seg]) begin : segment_loop
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if (ena[seg] == 0) begin
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some_empty = 1'b1;
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end
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end : segment_loop;
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end
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always_comb begin
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if (no_ena) begin
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send_idle = 1'b0;
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end else begin
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// generally either there is an EOP with some empty segments
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// or all empty segments on an unrotated bus. I'm not sure
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// what this implies on an rotated bus
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send_idle = no_eop & some_empty;
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end
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end
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// Calculate Pop ///////////
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//////////////////////////////////////////////////////////////////////////////////
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// After rotation figure out how far till eop
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logic [NUM_SEG-1:0] rot_xfer_now;
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// unrotate the values and calculate pop
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logic [NUM_SEG-1:0] xfer_now;
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logic [NUM_SEG-1:0] filler_seg;
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always_comb begin
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rot_xfer_now = '0;
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if (eop) begin
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for (int i = 0; i < NUM_SEG; i = i + 1) begin
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rot_xfer_now[i] = '1;
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if (rot_eop[i]) begin
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break;
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end
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end
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end
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if (send_idle)
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xfer_now = '0;
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else if (no_eop)
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xfer_now = '1;
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else
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// rotate left
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xfer_now = {rot_xfer_now,rot_xfer_now} >> (NUM_SEG - rot);
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end
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// Flush out valid segments with no enable
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assign filler_seg = ~ena & ~empty;
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assign pop = (xfer_now | filler_seg) & ~empty;
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// Calculate Rotate for the next clock ///////////
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//////////////////////////////////////////////////////////////////////////////////
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logic [$clog2(NUM_SEG)-1:0] next_rot;
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always_comb begin
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next_rot = 0;
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foreach (rot_empty[s]) begin
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if (~rot_empty[s] & lbus_rot[s].sop) begin
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next_rot = s;
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end
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end
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end
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always @(posedge axis.clk)
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begin
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if(axis.rst) begin
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rot <= '0;
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//no valid data on any segment
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end else if( no_ena ) begin
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rot <= '0;
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// If EOP, but no SoP
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end else if( no_sop & ~no_eop & some_empty) begin
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rot <= '0;
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// If SOP, accumulate rotation to push to seg 0
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end else if( ~no_sop ) begin
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rot <= rot+next_rot;
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end
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end
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// Rotation of segments from fifo output ///////////
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//////////////////////////////////////////////////////////////////////////////////
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generate
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genvar b2,gseg2;
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begin : rotate_lbus
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//perform a bitwise rotation.
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for(b2 = 0; b2 < SEG_SHMEAR_WIDTH; b2=b2+1) begin
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logic [NUM_SEG-1:0] slice, slice_rotated;
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//copy a horizontal slice across the segments
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for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
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assign slice[gseg2] = lbus_fout[gseg2][b2];
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end
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// rotate the slice (should make SEG_SHMEAR_WIDTH copies of NUM_SEG to 1 mux)
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assign slice_rotated = {slice,slice} >> rot; //rotate_right
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// Copy slice back to the struct
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for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
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assign lbus_rot[gseg2][b2] = slice_rotated[gseg2];
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end
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end
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end : rotate_lbus
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endgenerate
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always_comb begin : rotate_data_valid
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rot_empty = {empty,empty} >> rot; //rotate_right
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end : rotate_data_valid
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// LBUS out DFF /////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// This pipe stage is mainly to allow suming MTY bits and to add space for
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// Vivado to try to pipeline the output
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// post rotation lbus signals
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lbus_t lbus_out [NUM_SEG-1:0];
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logic [NUM_SEG-1:0] axi_seg_valid;
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always_ff @(posedge axis.clk)
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begin
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if (axis.rst) begin
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foreach (lbus_out[seg]) begin : segment_loop
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lbus_out[seg] <= '0;
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end
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axi_seg_valid <= '0;
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end else begin
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lbus_out <= lbus_rot;
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if (send_idle)
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axi_seg_valid <= '0;
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else if (no_eop)
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axi_seg_valid <= '1;
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else
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axi_seg_valid <= rot_xfer_now;
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end
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end
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////////////////////////////////////////////////////////////////////////////
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// Generate AXI
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////////////////////////////////////////////////////////////////////////////
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logic [axis.DATA_WIDTH - 1:0] axis_tdata_w;
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logic [$clog2(axis.DATA_WIDTH/8) - 1:0] axis_tuser_bytes_w;
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logic [axis.DATA_WIDTH/8 - 1:0] axis_tkeep_w;
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logic [NUM_SEG-1:0] axis_tlast_w;
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logic [NUM_SEG-1:0] axis_tvalid_w;
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logic [NUM_SEG-1:0] axis_tuser_err_w;
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always_comb begin : axis_translate
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axis_tuser_bytes_w = 'd0; // init to zero before summing
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foreach (axis_tvalid_w[seg]) begin : segment_loop
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axis_tvalid_w[seg] = lbus_out[seg].ena & axi_seg_valid[seg];
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axis_tlast_w[seg] = lbus_out[seg].eop;
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axis_tuser_err_w[seg] = lbus_out[seg].err;
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// sum all the segment mty vectors
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if (lbus_out[seg].ena && axi_seg_valid[seg]) begin
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axis_tuser_bytes_w += SEG_DATA_WIDTH/8 - lbus_out[seg].mty;
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end
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// 512 bit word = 64 bytes = 4 X 128 bit(16 byte) segments
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// assign bytes : LbusOrder
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// S0 : S0B0..S0B15
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// S1 : S1B0..S1B15
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// S2 : S2B0..S2B15
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// S3 : S3B0..S3B15
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// AXI (swap Endianess on each segment)
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// AXI = S3B15..S3B0, S2B15..S2B0, S1B15..S1B0, S0B15..S0B0
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for(int b = 0; b < SEG_BYTES; b=b+1) begin : tdata_loop
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// ( 1 * 128 )-8- 0*8) 120+:8 = S0B0
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// ( 1 * 128 )-8- 1*8) 112+:8 = S0B1
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// ...
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// ( 1 * 128 )-8-14*8) 8+:8 = S0B14
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// ( 1 * 128 )-8-15*8) 0+:8 = S0B15
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////////////////////////////////////
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// ( 2 * 128 )-8- 0*8) 248+:8 = S1B0
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// ( 2 * 128 )-8- 1*8) 240+:8 = S1B1
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// ...
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// ( 2 * 128 )-8-14*8) 136+:8 = S1B14
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// ( 2 * 128 )-8-15*8) 128+:8 = S1B15
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////////////////////////////////////
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// ...
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////////////////////////////////////
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// ( 4 * 128 )-8- 0*8) 504+:8 = S3B0
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// ( 4 * 128 )-8- 1*8) 496+:8 = S3B1
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// ...
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// ( 4 * 128 )-8-14*8) 136+:8 = S3B14
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// ( 4 * 128 )-8-15*8) 384+:8 = S3B15
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axis_tdata_w[((seg+1)*axis.DATA_WIDTH/NUM_SEG-8-b*8) +: 8] = lbus_out[seg].data[b*8 +: 8];
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end : tdata_loop
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end : segment_loop
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end : axis_translate
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// convert bytes to keep
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always_comb begin
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axis_tkeep_w = '1;
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if (axis_tlast_w != 0 && axis_tuser_bytes_w != 0) begin
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foreach(axis_tkeep_w[b]) begin
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axis_tkeep_w[b] = axis_tuser_bytes_w > b;
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end
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end
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end
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//////////////////////////////////////////////////////////////////////////////////
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////////////////// AXIS output flop /////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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localparam AXIS_MTY_WIDTH = $clog2(axis.BYTES_PER_WORD);
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always_ff @(posedge axis.clk)
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begin
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if (axis.rst) begin
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axis.tdata <= '0;
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axis.tvalid <= 1'b0;
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axis.tlast <= 1'b0;
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axis.tuser <= '0;
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axis.tkeep <= '0;
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end else begin
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axis.tdata <= axis_tdata_w;
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axis.tvalid <= |axis_tvalid_w;
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axis.tlast <= |axis_tlast_w;
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if (axis.TKEEP == 1) begin
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axis.tkeep <= axis_tkeep_w;
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end else begin
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axis.tkeep <= 'X;
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end
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// trailing bytes in last word
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axis.tuser[AXIS_MTY_WIDTH-1:0] <= axis_tuser_bytes_w;
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// MSB is error
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axis.tuser[AXIS_MTY_WIDTH] <= |axis_tuser_err_w;
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end
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end
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endmodule
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