Martin Braun
6ef3795e42
- All RFNoC capable targets now require rfnoc_image_builder to be built - `make help` is updated for all targets to provide more useful and up-to-date information - The FPGA manual is also updated - All checked-in build artifacts are now removed from git - axi_ram_fifo.yml is updated to provide include path information (required for building N3xx BIST images, which use this) Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
157 lines
6.1 KiB
Makefile
157 lines
6.1 KiB
Makefile
#
|
|
# Copyright 2018 Ettus Research LLC
|
|
#
|
|
|
|
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
|
|
##-------------------
|
|
##USRP E31X FPGA Help
|
|
##-------------------
|
|
##Usage:
|
|
## rfnoc_image_builder -y <image core file> -t <target> -n <image core name>
|
|
##
|
|
## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
|
|
## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
|
|
## environment, and run Vivado to build a bitfile.
|
|
##
|
|
## There exist some special make targets which can be called directly like this:
|
|
##
|
|
## make <Targets> <Options>
|
|
##
|
|
##Output:
|
|
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
|
|
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts: Device tree source file
|
|
## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
|
|
|
|
# Base output directory for all builds.
|
|
BUILD_BASE_DIR ?= .
|
|
# Base directory for the build outputs.
|
|
BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
|
|
|
|
# Initialize a build seed. This can be changed to randomly affect build results.
|
|
BUILD_SEED ?= 0
|
|
DEFS += BUILD_SEED=$(BUILD_SEED)
|
|
|
|
# Set build option (check RTL, run synthesis, or do a full build)
|
|
ifndef TARGET
|
|
ifeq ($(CHECK), 1)
|
|
TARGET = rtl
|
|
else ifeq ($(SYNTH), 1)
|
|
TARGET = synth
|
|
else ifeq ($(IP_ONLY), 1)
|
|
TARGET = viv_ip
|
|
else
|
|
TARGET = bin
|
|
endif
|
|
endif
|
|
TOP ?= e31x
|
|
|
|
# vivado_build($1=Device, $2=Definitions)
|
|
vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
|
|
vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
|
|
|
|
# post_build($1=Device)
|
|
ifeq ($(TARGET),bin)
|
|
post_build = @\
|
|
mkdir -p $(BUILD_OUTPUT_DIR); \
|
|
echo "Exporting bitstream file..."; \
|
|
cp $(BUILD_DIR)/e31x.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
|
|
echo "Exporting build report..."; \
|
|
cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
|
|
echo "Build DONE ... $(1)";
|
|
else
|
|
post_build = @echo "Skipping bitfile export."
|
|
endif
|
|
|
|
##
|
|
##Supported Targets
|
|
##-----------------
|
|
##Reminder: Targets are built by calling
|
|
##
|
|
## $ rfnoc_image_builder -y <image core file.yml> -t <target name> -n <image core name>
|
|
##
|
|
##The following table lists all valid combinations:
|
|
##
|
|
##--------------------------|---------------|-------------------------|------------------
|
|
## Default Image core file | Target | Image core name | Description
|
|
##--------------------------|---------------|-------------------------|------------------
|
|
##e310_rfnoc_image_core.yml | E310_SG1 | usrp_e310_sg1_fpga | E310 speedgrade 1
|
|
##e310_rfnoc_image_core.yml | E310_SG1_IDLE | usrp_e310_sg1_idle_fpga | E310 speedgrade 1, idle image
|
|
##e310_rfnoc_image_core.yml | E310_SG3 | usrp_e310_sg3_fpga | E310 speedgrade 3
|
|
##e310_rfnoc_image_core.yml | E310_SG3_IDLE | usrp_e310_sg3_idle_fpga | E310 speedgrade 3, idle image
|
|
##
|
|
##Of course, a custom YAML file may be used.
|
|
##
|
|
|
|
check-variables:
|
|
ifndef IMAGE_CORE_NAME
|
|
$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
|
|
endif
|
|
ifndef BUILD_DIR
|
|
$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
|
|
endif
|
|
|
|
##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
|
|
E310_SG1_IDLE E3XX_idle: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
|
|
$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
|
|
$(call post_build,$@)
|
|
|
|
##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
|
|
E310_SG3_IDLE E3XX_idle_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
|
|
$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
|
|
$(call post_build,$@)
|
|
|
|
##E310_SG1: Build USRP E3XX (Speed Grade 1).
|
|
E310_SG1 E310: check-variables E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
|
|
$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
|
|
$(call post_build,$@)
|
|
|
|
##E310_SG3: Build USRP E3XX (Speed Grade 3).
|
|
E310_SG3 E310_sg3: check-variables E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
|
|
$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
|
|
$(call post_build,$@)
|
|
|
|
$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
|
|
-mkdir -p $(BUILD_OUTPUT_DIR)
|
|
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
|
|
|
|
##
|
|
##Other Make Targets (these should be called directly)
|
|
##----------------------------------------------------
|
|
|
|
##E310_SG1_IP: Build IP for E310_SG1 only. Use the -j option to build multiple IP blocks simultaneously.
|
|
E310_SG1_IP:
|
|
+$(call vivado_ip,E310_SG1,E310_SG1=1)
|
|
|
|
##E310_SG3_IP: Build IP for E310_SG3 only. Use the -j option to build multiple IP blocks simultaneously.
|
|
E310_SG3_IP:
|
|
+$(call vivado_ip,E310_SG3,E310_SG3=1)
|
|
|
|
clean: ##Clean up all target build outputs.
|
|
@echo "Cleaning targets..."
|
|
@rm -rf $(BUILD_BASE_DIR)/build-E3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
|
|
@rm -rf $(BUILD_OUTPUT_DIR)
|
|
|
|
cleanall: ##Clean up all target and ip build outputs.
|
|
@echo "Cleaning targets and IP..."
|
|
@rm -rf build-ip
|
|
@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
|
|
@rm -rf $(BUILD_OUTPUT_DIR)
|
|
|
|
help: ##Show this help message.
|
|
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
|
|
|
|
##
|
|
##Supported Options
|
|
##-----------------
|
|
##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build.
|
|
## Note: The RFNoC image core must also be configured to use DRAM.
|
|
##GUI=1 Launch the build in the Vivado GUI.
|
|
##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
|
|
##CHECK=1 Launch the syntax checker instead of building a bitfile.
|
|
##IP_ONLY=1 Launch the build but stop after IP generation.
|
|
##SYNTH=1 Launch the build but stop after synthesis.
|
|
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
|
|
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
|
|
|
|
.PHONY: all clean cleanall help
|