88 lines
3.2 KiB
Verilog
88 lines
3.2 KiB
Verilog
//
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// Copyright 2013-2014 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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module timekeeper_legacy
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#(parameter SR_TIME_HI = 0,
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parameter SR_TIME_LO = 1,
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parameter SR_TIME_CTRL = 2,
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parameter INCREMENT = 64'h1)
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(input clk, input reset, input pps, input sync_in, input strobe,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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output reg [63:0] vita_time, output reg [63:0] vita_time_lastpps,
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output reg sync_out);
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//////////////////////////////////////////////////////////////////////////
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// timer settings for this module
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//////////////////////////////////////////////////////////////////////////
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wire [63:0] time_at_next_event;
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wire set_time_pps, set_time_now, set_time_sync;
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wire cmd_trigger;
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setting_reg #(.my_addr(SR_TIME_HI), .width(32)) sr_time_hi
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(time_at_next_event[63:32]), .changed());
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setting_reg #(.my_addr(SR_TIME_LO), .width(32)) sr_time_lo
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(time_at_next_event[31:0]), .changed());
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setting_reg #(.my_addr(SR_TIME_CTRL), .width(3)) sr_ctrl
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out({set_time_sync, set_time_pps, set_time_now}), .changed(cmd_trigger));
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//////////////////////////////////////////////////////////////////////////
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// PPS edge detection logic
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//////////////////////////////////////////////////////////////////////////
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reg pps_del, pps_del2;
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always @(posedge clk)
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{pps_del2,pps_del} <= {pps_del, pps};
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wire pps_edge = !pps_del2 & pps_del;
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//////////////////////////////////////////////////////////////////////////
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// arm the trigger to latch a new time when the ctrl register is written
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//////////////////////////////////////////////////////////////////////////
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reg armed;
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wire time_event = armed && ((set_time_now) || (set_time_pps && pps_edge) || (set_time_sync && sync_in));
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always @(posedge clk) begin
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if (reset) armed <= 1'b0;
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else if (cmd_trigger) armed <= 1'b1;
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else if (time_event) armed <= 1'b0;
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end
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//////////////////////////////////////////////////////////////////////////
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// vita time tracker - update every tick or when we get an "event"
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk) begin
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sync_out <= 1'b0;
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if(reset) begin
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vita_time <= 64'h0;
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end else begin
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if (time_event) begin
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sync_out <= 1'b1;
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vita_time <= time_at_next_event;
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end else if (strobe) begin
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vita_time <= vita_time + INCREMENT;
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end
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end
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end
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//////////////////////////////////////////////////////////////////////////
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// track the time at last pps so host can detect the pps
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk)
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if(reset)
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vita_time_lastpps <= 64'h0;
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else if(pps_edge)
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if(time_event)
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vita_time_lastpps <= time_at_next_event;
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else
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vita_time_lastpps <= vita_time + INCREMENT;
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endmodule // timekeeper_legacy
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