282 lines
9.9 KiB
VHDL
282 lines
9.9 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: tb_rf_nco_reset
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--
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-- Description:
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--
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-- Self-checking testbench for NCO reset sequencing.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity tb_rf_nco_reset is
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end tb_rf_nco_reset;
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architecture RTL of tb_rf_nco_reset is
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signal cAdc0xNcoUpdateReq : std_logic;
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signal cAdc2xNcoUpdateReq : std_logic;
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signal cDac0xNcoUpdateReq : std_logic;
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signal cDac0xSysrefIntGating : std_logic;
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signal cDac0xSysrefIntReenable : std_logic;
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signal cDac1xNcoUpdateReq : std_logic;
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signal cNcoPhaseRst : std_logic;
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signal cNcoUpdateEn : std_logic_vector(5 downto 0);
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signal dNcoResetDone : std_logic;
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signal cDac0xNcoUpdateBusy : std_logic_vector(1 downto 0) := "00";
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signal dStartNcoReset : std_logic := '0';
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signal cAdc0xNcoUpdateBusy : std_logic := '0';
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signal cAdc2xNcoUpdateBusy : std_logic := '0';
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signal cDac1xNcoUpdateBusy : std_logic := '0';
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signal cSysref_ms, cSysref : std_logic := '0';
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signal cSysrefDlyd : std_logic_vector(1 downto 0) := "00";
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signal cDac0xSysrefIntGatingDlyd : std_logic := '0';
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signal cNcoPhaseRstDlyd : std_logic_vector(2 downto 0) := "000";
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signal cWrCount : integer := 0;
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type RfdcNcoState_t is (Idle, GateSysref, UpdateReq, CheckUpdate,
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SysrefEn, WaitForSysref, ResetDone);
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signal cRfdcNcoState : RfdcNcoState_t := Idle;
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signal StopSim : boolean;
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constant kConfigClkPer : time := 25 ns;
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-- SYSREF period is 2.5 MHz.
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constant kSysrefPer : time := 400 ns;
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-- DataClk period is 125 MHz and generated from the same clocking chip that
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-- generated SYSREF and are related.
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constant kDataClkPer : time := kSysrefPer/50;
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signal ConfigClk : std_logic := '0';
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signal DataClk : std_logic := '0';
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signal dSysref : std_logic := '0';
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procedure DataClkWait(X : positive := 1) is
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begin
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for i in 1 to X loop
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wait until rising_edge(DataClk);
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end loop;
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end procedure DataClkWait;
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procedure ConfigClkWait(X : positive := 1) is
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begin
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for i in 1 to X loop
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wait until rising_edge(ConfigClk);
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end loop;
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end procedure ConfigClkWait;
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procedure SysrefWait(X : positive := 1) is
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begin
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for i in 1 to X loop
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wait until rising_edge(dSysref);
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end loop;
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end procedure SysrefWait;
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begin
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ConfigClk <= not ConfigClk after kConfigClkPer/2 when not StopSim else '0';
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DataClk <= not DataClk after kDataClkPer/2 when not StopSim else '0';
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dSysref <= not dSysref after kSysrefPer/2 when not StopSim else '0';
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-- Both cNcoPhaseRst and cNcoUpdateEn are constants in the DUT.
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dut: entity WORK.rf_nco_reset (RTL)
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port map (
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ConfigClk => ConfigClk,
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DataClk => DataClk,
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dSysref => dSysref,
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dStartNcoReset => dStartNcoReset,
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cDac0xNcoUpdateBusy => cDac0xNcoUpdateBusy,
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cDac0xNcoUpdateReq => cDac0xNcoUpdateReq,
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cDac0xSysrefIntGating => cDac0xSysrefIntGating,
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cDac0xSysrefIntReenable => cDac0xSysrefIntReenable,
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cDac1xNcoUpdateBusy => cDac1xNcoUpdateBusy,
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cDac1xNcoUpdateReq => cDac1xNcoUpdateReq,
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cAdc0xNcoUpdateBusy => cAdc0xNcoUpdateBusy,
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cAdc0xNcoUpdateReq => cAdc0xNcoUpdateReq,
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cAdc2xNcoUpdateBusy => cAdc2xNcoUpdateBusy,
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cAdc2xNcoUpdateReq => cAdc2xNcoUpdateReq,
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cNcoPhaseRst => cNcoPhaseRst,
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cNcoUpdateEn => cNcoUpdateEn,
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dNcoResetDone => dNcoResetDone
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);
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main: process
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-- Procedure to sweep the entire SYSREF period.
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-- When we strobe dStartNcoReset for one DataClk cycle. NCO reset sequence
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-- is initiated. In this procedure, we sweep the dStartNcoReset strobe the
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-- entire SYSREF cycle.
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procedure SysrefSweep is
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constant kSysrefInRfCycles : integer := kSysrefPer/kDataClkPer;
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begin
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for i in 1 to kSysrefInRfCycles loop
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wait until cDac0xSysrefIntGating = '0' for 1 us;
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assert cDac0xSysrefIntGating = '0'
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report "NCO phase reset does not de-assert"
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severity error;
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SysrefWait;
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DataClkWait(i);
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dStartNcoReset <= '0';
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DataClkWait;
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dStartNcoReset <= '1';
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DataClkWait;
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dStartNcoReset <= '0';
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-- Wait for a minimum of 3 SYSREF period. 1 SYSREF edge is used to
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-- initiate NCO reset, 1 SYSREF edge is used to re-enable SYSREF and 1
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-- SYSREF edge is used by RFDC to reset all NCOs.
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SysrefWait(3);
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end loop;
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end procedure;
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begin
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-- Strobe dStartNcoReset across entire SYSREF period.
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SysrefSweep;
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-- Wait for a minimum of 3 SYSREF cycles to make sure NCO reset is complete.
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SysrefWait(3);
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StopSim <= true;
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wait;
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end process;
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-- Process to mimic RFDC NCO reset
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-- This state machine is based of "NCO frequency hopping" section in PG269
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-- (v2.2). Refer to multi-mode subsection for more details.
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MimicRfdc: process(ConfigClk)
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begin
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if falling_edge(ConfigClk) then
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cRfdcNcoState <= Idle;
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case cRfdcNcoState is
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-- Wait until SYSREF internal gating is asserted.
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when Idle =>
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cWrCount <= 0;
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if cDac0xSysrefIntGating = '1' then
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cRfdcNcoState <= GateSysref;
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end if;
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-- Change cDac0xNcoUpdateBusy to "11" to indicate SYSREF is gated
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-- internally when NCO update is requested on DAC tile 228.
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-- cDac0xNcoUpdateBusy(0) is set to '1', the SYSREF is gated and
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-- cDac0xNcoUpdateBusy(1) is set to '1', to indicate the NCO reset
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-- process has started, but not complete.
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when GateSysref =>
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cRfdcNcoState <= GateSysref;
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if cDac0xNcoUpdateReq = '1' then
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cRfdcNcoState <= UpdateReq;
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cDac0xNcoUpdateBusy <= "11";
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end if;
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-- If NCO reset is requested on other tiles, assert NCO update busy on
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-- other tiles as well.
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when UpdateReq =>
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cRfdcNcoState <= CheckUpdate;
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cDac1xNcoUpdateBusy <= cDac1xNcoUpdateReq;
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cAdc0xNcoUpdateBusy <= cAdc0xNcoUpdateReq;
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cAdc2xNcoUpdateBusy <= cAdc2xNcoUpdateReq;
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-- It takes 5 clock cycles to update each RFDC internal registers with
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-- the used request change. In rf_nco_reset entity, we only want to
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-- reset the NCO, which is a single bit. So, it should take only 5
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-- ConfigClk for the update. When the internal register is updated, set
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-- cDac0xNcoUpdateBusy(0) to '0'.
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when CheckUpdate =>
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cRfdcNcoState <= CheckUpdate;
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if cWrCount > 4 then
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cRfdcNcoState <= SysrefEn;
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cDac0xNcoUpdateBusy <= "10"; --Indicates that SYSREF is gated.
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cDac1xNcoUpdateBusy <= '0';
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cAdc0xNcoUpdateBusy <= '0';
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cAdc2xNcoUpdateBusy <= '0';
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end if;
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cWrCount <= cWrCount + 1;
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-- Wait until internal SYSREF gating is disabled.
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when SysrefEn =>
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cWrCount <= 0;
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cRfdcNcoState <= SysrefEn;
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if cDac0xSysrefIntReenable = '1' then
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if cSysrefDlyd(0) = '0' and cSysref = '1' then
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cDac0xNcoUpdateBusy <= "00"; --Indicates that NCO reset is complete.
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cRfdcNcoState <= ResetDone;
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else
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cRfdcNcoState <= WaitForSysref;
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end if;
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end if;
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-- NCO reset is done on the rising edge of SYSREF. When NCO reset is
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-- complete, set cDac0xNcoUpdateBusy(1) to '0'.
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when WaitForSysref =>
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cRfdcNcoState <= WaitForSysref;
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if cSysrefDlyd(0) = '0' and cSysref = '1' then
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cDac0xNcoUpdateBusy <= "00"; --Indicates that NCO reset is complete.
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cRfdcNcoState <= ResetDone;
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end if;
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-- Wait in this state, until the next NCO reset is requested.
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when ResetDone =>
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cRfdcNcoState <= ResetDone;
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if cDac0xSysrefIntGating = '1' then
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cRfdcNcoState <= GateSysref;
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end if;
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end case;
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end if;
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end process;
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-- SYSREF clock crossing from DataClk to ConfigClk and some pipelines.
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ConfigClkSysref: process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
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cSysref_ms <= dSysref;
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cSysref <= cSysref_ms;
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cSysrefDlyd <= cSysrefDlyd(cSysrefDlyd'high-1) & cSysref;
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cDac0xSysrefIntGatingDlyd <= cDac0xSysrefIntGating;
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cNcoPhaseRstDlyd <= cNcoPhaseRstDlyd(cNcoPhaseRstDlyd'high downto 1)
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& cDac0xNcoUpdateBusy(1);
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end if;
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end process;
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-- Assertions
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process(ConfigClk)
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begin
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if falling_edge(ConfigClk) then
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--Check if cNcoPhaseRst is a constant of '1'.
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assert cNcoPhaseRst = '1'
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report "NCO phase reset signal should be constant."
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severity error;
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-- Check if cNcoUpdateEn is a constant of "100000".
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assert cNcoUpdateEn = "100000"
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report "NCO phase reset signal should be constant."
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severity error;
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-- Check if NCO reset was requested on the rising edge of SYSREF.
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if cDac0xSysrefIntGating = '1' and cDac0xSysrefIntGatingDlyd = '0' then
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assert cSysrefDlyd = "01"
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report "NCO reset did not start on SYSREF rising edge"
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severity error;
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end if;
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-- We wait for couple of clock cycles after NCO done signal is toggled in
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-- from the RFDC. RFDC uses cDac0xNcoUpdateBusy(1) to indicate NCO reset
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-- process is done. It is important to wait a minimum of three clock
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-- cycles before this check is done. This wait is needed for clock
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-- crossing.
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if cNcoPhaseRstDlyd(2) = '1' and cNcoPhaseRstDlyd(1) = '0' then
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assert dNcoResetDone = '1'
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report "NCO Reset done should have been asserted after NCO " &
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"reset request is de-asserted"
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severity error;
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end if;
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end if;
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end process;
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end RTL;
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