32 lines
1.3 KiB
Systemverilog
32 lines
1.3 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: gpio_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// BASE_WINDOW_GPIO : 0x0 (zbx_top_cpld.v)
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// DB_CONTROL_WINDOW_GPIO : 0x1000 (zbx_top_cpld.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group GPIO_REGMAP_WINDOWS
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//===============================================================================
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// BASE_WINDOW_GPIO Window (from zbx_top_cpld.v)
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localparam BASE_WINDOW_GPIO = 'h0; // Window Offset
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localparam BASE_WINDOW_GPIO_SIZE = 'h20; // size in bytes
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// DB_CONTROL_WINDOW_GPIO Window (from zbx_top_cpld.v)
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localparam DB_CONTROL_WINDOW_GPIO = 'h1000; // Window Offset
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localparam DB_CONTROL_WINDOW_GPIO_SIZE = 'h5000; // size in bytes
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