steviez
3bbc81bb44
This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices. Original-commit: ae2b9bf7aeea6f8f98f6dacffdfc018d87107927
30 lines
477 B
Devicetree
30 lines
477 B
Devicetree
// SPDX-License-Identifier: GPL-2.0 OR X11
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/*
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* Copyright (c) 2017 National Instruments Corp
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*/
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/dts-v1/;
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/plugin/;
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#include "n320-fpga.dtsi"
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&fpga_full {
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uio@40004000 {
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compatible = "usrp-uio";
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reg = <0x40004000 0x1000>;
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reg-names = "misc-auro-regs0";
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status = "okay";
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};
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uio@4000c000 {
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compatible = "usrp-uio";
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reg = <0x4000c000 0x1000>;
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reg-names = "misc-auro-regs1";
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status = "okay";
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};
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};
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#include "n320-common.dtsi"
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#include "dma-common.dtsi"
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