Wade Fife
14dc3950cf
This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data); Original-commit: fc895feacb8dde3b02c9a4eccb4b4f4a654f2881
249 lines
7.1 KiB
Systemverilog
249 lines
7.1 KiB
Systemverilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: PkgChdrUtils
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//
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// Description: Various types, constants, and functions for interacting with
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// the RFNoC CHDR bus infrastructure.
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//
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package PkgChdrUtils;
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import PkgChdrData::*;
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//---------------------------------------------------------------------------
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// Type Definitions
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//---------------------------------------------------------------------------
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//----------------------
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// AXIS-CHDR Definitions
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//----------------------
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// Expose the CHDR word and item/sample data types and methods in the
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// ChdrData class. The width of these types is a class parameter.
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export PkgChdrData::ChdrData;
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// CHDR header fields
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typedef enum bit [2:0] {
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CHDR_MANAGEMENT = 3'd0,
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CHDR_STRM_STATUS = 3'd1,
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CHDR_STRM_CMD = 3'd2,
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CHDR_RESERVED_0 = 3'd3,
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CHDR_CONTROL = 3'd4,
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CHDR_RESERVED_1 = 3'd5,
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CHDR_DATA_NO_TS = 3'd6,
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CHDR_DATA_WITH_TS = 3'd7
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} chdr_pkt_type_t; // CHDR Packet Type
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typedef bit [ 5:0] chdr_vc_t; // CHDR Virtual Channel field
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typedef bit [ 0:0] chdr_eob_t; // CHDR End of Burst field
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typedef bit [ 0:0] chdr_eov_t; // CHDR End of Vector field
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typedef bit [ 4:0] chdr_num_mdata_t; // CHDR Num Metadata field
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typedef bit [15:0] chdr_seq_num_t; // CHDR SeqNum field
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typedef bit [15:0] chdr_length_t; // CHDR Length field
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typedef bit [15:0] chdr_epid_t; // CHDR EPID field
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typedef bit [63:0] chdr_timestamp_t; // CHDR Timestamp field
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// CHDR Context Field Identifiers
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typedef enum bit [3:0] {
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CONTEXT_FIELD_HDR = 4'd0,
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CONTEXT_FIELD_HDR_TS = 4'd1,
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CONTEXT_FIELD_TS = 4'd2,
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CONTEXT_FIELD_MDATA = 4'd3
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} chdr_context_type_t;
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//----------------------
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// AXIS-Ctrl Definitions
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//----------------------
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// The fundamental unit of the AXIS-Ctrl (control) bus, which is always 32 bits
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typedef logic [31:0] ctrl_word_t;
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typedef enum bit [3:0] {
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CTRL_OP_SLEEP = 4'd0,
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CTRL_OP_WRITE = 4'd1,
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CTRL_OP_READ = 4'd2,
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CTRL_OP_WRITE_READ = 4'd3,
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CTRL_OP_RESERVED_0 = 4'd4,
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CTRL_OP_RESERVED_1 = 4'd5,
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CTRL_OP_RESERVED_2 = 4'd6,
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CTRL_OP_RESERVED_3 = 4'd7,
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CTRL_OP_RESERVED_4 = 4'd8,
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CTRL_OP_RESERVED_5 = 4'd9
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} ctrl_opcode_t; // Control OpCode Type
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typedef enum bit [1:0] {
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CTRL_STS_OKAY = 2'd0,
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CTRL_STS_CMDERR = 2'd1,
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CTRL_STS_TSERR = 2'd2,
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CTRL_STS_WARNING = 2'd3
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} ctrl_status_t; // Control OpCode Type
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typedef bit [5:0] ctrl_seq_num_t; // AXIS-Ctrl SeqNum field
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typedef bit [3:0] ctrl_num_data_t; // AXIS-Ctrl NumData field
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typedef bit [9:0] ctrl_port_t; // AXIS-Ctrl source/destination port field
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typedef bit [3:0] ctrl_byte_en_t; // AXIS-Ctrl ByteEnable field
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typedef bit [19:0] ctrl_address_t; // AXIS-Ctrl Address field
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//-------------------------------
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// CHDR Type-Specific Definitions
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//-------------------------------
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// CHDR Status packet fields
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typedef enum bit [3:0] {
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STRS_OKAY = 4'd0,
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STRS_CMDERR = 4'd1,
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STRS_SEQERR = 4'd2,
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STRS_DATAERR = 4'd3,
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STRS_RTERR = 4'd4
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} chdr_strs_status_t; // CHDR stream status packet status field
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// CHDR Control packet fields
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typedef enum bit [3:0] {
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STRC_INIT = 4'd0,
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STRC_PING = 4'd1,
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STRC_RESYNC = 4'd2
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} chdr_strc_opcode_t; // CHDR stream command packet opcode filed
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// CHDR Management packet field
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typedef enum bit [2:0] {
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CHDR_W_64 = 3'd0,
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CHDR_W_128 = 3'd1,
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CHDR_W_256 = 3'd2,
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CHDR_W_512 = 3'd3,
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CHDR_W_INVALID = 3'd7
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} chdr_mgmt_width_t; // CHDR management packet CHDR Width field
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function automatic chdr_mgmt_width_t translate_chdr_w(int bitwidth);
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case (bitwidth)
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64: return CHDR_W_64;
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128: return CHDR_W_128;
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256: return CHDR_W_256;
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512: return CHDR_W_512;
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default: return CHDR_W_INVALID;
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endcase
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endfunction : translate_chdr_w
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typedef enum bit [7:0] {
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MGMT_OP_NOP = 8'd0,
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MGMT_OP_ADVERTISE = 8'd1,
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MGMT_OP_SEL_DEST = 8'd2,
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MGMT_OP_RETURN = 8'd3,
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MGMT_OP_INFO_REQ = 8'd4,
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MGMT_OP_INFO_RESP = 8'd5,
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MGMT_OP_CFG_WR_REQ = 8'd6,
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MGMT_OP_CFG_RD_REQ = 8'd7,
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MGMT_OP_CFG_RD_RESP = 8'd8
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} chdr_mgmt_opcode_t; // CHDR management packet OpCode field
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//---------------------------------------------------------------------------
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// Packet Data Structures
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//---------------------------------------------------------------------------
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// CHDR packet header
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typedef struct packed {
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chdr_vc_t vc;
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chdr_eob_t eob;
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chdr_eov_t eov;
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chdr_pkt_type_t pkt_type;
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chdr_num_mdata_t num_mdata;
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chdr_seq_num_t seq_num;
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chdr_length_t length;
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chdr_epid_t dst_epid;
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} chdr_header_t;
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// AXIS-Ctrl packet header
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typedef struct packed {
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// Word 1
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bit [ 5:0] _rsvd_0;
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ctrl_port_t rem_dst_port;
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chdr_epid_t rem_dst_epid;
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// Word 0
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bit is_ack;
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bit has_time;
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ctrl_seq_num_t seq_num;
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ctrl_num_data_t num_data;
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ctrl_port_t src_port;
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ctrl_port_t dst_port;
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} axis_ctrl_header_t;
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// AXIS-Ctrl packet header
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typedef struct packed {
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ctrl_status_t status;
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bit [ 1:0] _rsvd_0;
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ctrl_opcode_t op_code;
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bit [ 3:0] byte_enable;
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bit [19:0] address;
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} ctrl_op_word_t;
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// Ctrl packet header when in the payload of a CHDR packet
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typedef struct packed {
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bit [15:0] _rsvd_0;
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chdr_epid_t src_epid;
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bit is_ack;
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bit has_time;
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ctrl_seq_num_t seq_num;
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ctrl_num_data_t num_data;
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ctrl_port_t src_port;
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ctrl_port_t dst_port;
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} chdr_ctrl_header_t;
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// CHDR stream status packet payload
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typedef struct packed {
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// Word 3
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bit [47:0] status_info;
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bit [15:0] buff_info;
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// Word 2
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bit [63:0] xfer_count_bytes;
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// Word 1
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bit [39:0] xfer_count_pkts;
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bit [23:0] capacity_pkts;
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// Word 0
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bit [39:0] capacity_bytes;
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bit [ 3:0] _rsvd_0;
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chdr_strs_status_t status;
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chdr_epid_t src_epid;
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} chdr_str_status_t;
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// CHDR stream command packet payload
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typedef struct packed {
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// Word 1
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bit [63:0] num_bytes;
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// Word 0
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bit [39:0] num_pkts;
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bit [ 3:0] op_data;
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chdr_strc_opcode_t op_code;
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chdr_epid_t src_epid;
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} chdr_str_command_t;
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// CHDR management packet header
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typedef struct packed {
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bit [15:0] prot_ver;
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chdr_mgmt_width_t chdr_width;
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bit [18:0] _rsvd_0;
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bit [ 9:0] num_hops;
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chdr_epid_t src_epid;
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} chdr_mgmt_header_t;
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// CHDR management packet operation
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typedef struct packed {
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bit [47:0] op_payload;
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chdr_mgmt_opcode_t op_code;
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bit [ 7:0] ops_pending;
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} chdr_mgmt_op_t;
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// CHDR management packet
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typedef struct {
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chdr_mgmt_header_t header;
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chdr_mgmt_op_t ops[$];
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} chdr_mgmt_t;
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endpackage : PkgChdrUtils
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