Wade Fife
b0c8336087
This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight. Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
329 lines
13 KiB
Verilog
329 lines
13 KiB
Verilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_switchboard
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//
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// Description:
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//
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// The Switchboard RFNoC block routes any input CHDR stream to any output port.
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// Routing is 1 to 1, that is, an input port can only be connected to one
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// output port, and vice versa. Data sent on disconnected inputs will stall.
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//
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// Input Port Output Port
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// ┌───────┐ ┌───────┐
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// │ ├────────────┤ │
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// 0 ──┤ Demux │ ┌───────┤ Mux ├─ 0
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// │ ├─┐ │ ┌────┤ │
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// └───────┘ │ │ │ └───────┘
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// ┌───────┐ │ │ │
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// │ ├─┼──┘ │ ┌───────┐
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// 1 ──┤ Demux │ └─────┼────┤ │
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// │ ├───────┼────┤ Mux ├─ 1
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// └───────┘ │ ┌─┤ │
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// ┌───────┐ │ │ └───────┘
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// │ ├───────┘ │
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// 2 ──┤ Demux │ │
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// │ ├──────────┘
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// └───────┘
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS-CHDR data bus width
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// MTU : Maximum transmission unit (i.e., maximum packet size in
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// CHDR words is 2**MTU).
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// NUM_INPUTS : The number of input ports
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// NUM_OUTPUTS : The number of output ports
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//
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`default_nettype none
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module rfnoc_block_switchboard #(
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parameter [9:0] THIS_PORTID = 10'd0,
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parameter CHDR_W = 64,
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parameter [5:0] MTU = 10,
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parameter NUM_INPUTS = 1,
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parameter NUM_OUTPUTS = 1
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)(
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// RFNoC Framework Clocks and Resets
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input wire rfnoc_chdr_clk,
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input wire rfnoc_ctrl_clk,
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// RFNoC Backend Interface
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status,
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// AXIS-CHDR Input Ports (from framework)
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input wire [(NUM_INPUTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
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input wire [(NUM_INPUTS)-1:0] s_rfnoc_chdr_tlast,
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input wire [(NUM_INPUTS)-1:0] s_rfnoc_chdr_tvalid,
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output wire [(NUM_INPUTS)-1:0] s_rfnoc_chdr_tready,
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// AXIS-CHDR Output Ports (to framework)
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output wire [(NUM_OUTPUTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire [(NUM_OUTPUTS)-1:0] m_rfnoc_chdr_tlast,
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output wire [(NUM_OUTPUTS)-1:0] m_rfnoc_chdr_tvalid,
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input wire [(NUM_OUTPUTS)-1:0] m_rfnoc_chdr_tready,
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// AXIS-Ctrl Input Port (from framework)
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Output Port (to framework)
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready
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);
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//---------------------------------------------------------------------------
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// Signal Declarations
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//---------------------------------------------------------------------------
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// Clocks and Resets
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wire ctrlport_clk;
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wire ctrlport_rst;
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wire axis_chdr_clk;
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wire axis_chdr_rst;
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// CtrlPort Master
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wire m_ctrlport_req_wr;
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wire m_ctrlport_req_rd;
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wire [19:0] m_ctrlport_req_addr;
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wire [31:0] m_ctrlport_req_data;
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reg m_ctrlport_resp_ack;
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reg [31:0] m_ctrlport_resp_data;
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// Framework to User Logic: in
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wire [NUM_INPUTS*CHDR_W-1:0] m_in_chdr_tdata;
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wire [NUM_INPUTS-1:0] m_in_chdr_tlast;
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wire [NUM_INPUTS-1:0] m_in_chdr_tvalid;
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wire [NUM_INPUTS-1:0] m_in_chdr_tready;
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// User Logic to Framework: out
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wire [NUM_OUTPUTS*CHDR_W-1:0] s_out_chdr_tdata;
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wire [NUM_OUTPUTS-1:0] s_out_chdr_tlast;
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wire [NUM_OUTPUTS-1:0] s_out_chdr_tvalid;
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wire [NUM_OUTPUTS-1:0] s_out_chdr_tready;
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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noc_shell_switchboard #(
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.CHDR_W (CHDR_W),
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.THIS_PORTID (THIS_PORTID),
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.MTU (MTU),
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.NUM_INPUTS (NUM_INPUTS),
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.NUM_OUTPUTS (NUM_OUTPUTS)
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) noc_shell_switchboard_i (
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//---------------------
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// Framework Interface
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//---------------------
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// Clock Inputs
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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// Reset Outputs
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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// RFNoC Backend Interface
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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// CHDR Input Ports (from framework)
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
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// CHDR Output Ports (to framework)
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
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// AXIS-Ctrl Input Port (from framework)
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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// AXIS-Ctrl Output Port (to framework)
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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//---------------------
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// Client Interface
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//---------------------
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// CtrlPort Clock and Reset
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.ctrlport_clk (ctrlport_clk),
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.ctrlport_rst (ctrlport_rst),
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// CtrlPort Master
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.m_ctrlport_req_wr (m_ctrlport_req_wr),
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.m_ctrlport_req_rd (m_ctrlport_req_rd),
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.m_ctrlport_req_addr (m_ctrlport_req_addr),
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.m_ctrlport_req_data (m_ctrlport_req_data),
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.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
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.m_ctrlport_resp_data (m_ctrlport_resp_data),
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// AXIS-CHDR Clock and Reset
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.axis_chdr_clk (axis_chdr_clk),
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.axis_chdr_rst (axis_chdr_rst),
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// AXIS-CHDR to User Logic
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.m_in_chdr_tdata (m_in_chdr_tdata),
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.m_in_chdr_tlast (m_in_chdr_tlast),
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.m_in_chdr_tvalid (m_in_chdr_tvalid),
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.m_in_chdr_tready (m_in_chdr_tready),
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// AXIS-CHDR from User Logic
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.s_out_chdr_tdata (s_out_chdr_tdata),
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.s_out_chdr_tlast (s_out_chdr_tlast),
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.s_out_chdr_tvalid (s_out_chdr_tvalid),
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.s_out_chdr_tready (s_out_chdr_tready)
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);
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//---------------------------------------------------------------------------
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// Registers
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//---------------------------------------------------------------------------
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`include "rfnoc_block_switchboard_regs.vh"
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localparam INPUT_W = (NUM_INPUTS < 3) ? 1 : $clog2(NUM_INPUTS);
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localparam OUTPUT_W = (NUM_OUTPUTS < 3) ? 1 : $clog2(NUM_OUTPUTS);
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localparam MAX_W = (INPUT_W > OUTPUT_W) ? INPUT_W : OUTPUT_W;
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reg [NUM_INPUTS*OUTPUT_W-1:0] reg_demux_select = 0;
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reg [NUM_OUTPUTS*INPUT_W-1:0] reg_mux_select = 0;
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wire [MAX_W-1:0] addr_port;
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wire [SWITCH_ADDR_W-1:0] addr_offset;
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assign addr_port =
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(NUM_OUTPUTS < 2) ? 0 : m_ctrlport_req_addr[SWITCH_ADDR_W +: MAX_W];
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assign addr_offset = m_ctrlport_req_addr[0 +: SWITCH_ADDR_W];
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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m_ctrlport_resp_ack <= 0;
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m_ctrlport_resp_data <= 'bX;
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reg_demux_select <= 0;
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reg_mux_select <= 0;
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end else begin
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// Default assignments
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m_ctrlport_resp_ack <= 0;
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m_ctrlport_resp_data <= 0;
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// Handle register reads
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if (m_ctrlport_req_rd) begin
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m_ctrlport_resp_ack <= 1;
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case (addr_offset)
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REG_DEMUX_SELECT : m_ctrlport_resp_data[0 +: OUTPUT_W]
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<= reg_demux_select[addr_port*OUTPUT_W +: OUTPUT_W];
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REG_MUX_SELECT : m_ctrlport_resp_data[0 +: INPUT_W]
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<= reg_mux_select[addr_port*INPUT_W +: INPUT_W];
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endcase
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// Handle register writes
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end else if (m_ctrlport_req_wr) begin
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m_ctrlport_resp_ack <= 1;
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case (addr_offset)
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REG_DEMUX_SELECT : reg_demux_select[addr_port*OUTPUT_W +: OUTPUT_W]
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<= m_ctrlport_req_data[0 +: OUTPUT_W];
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REG_MUX_SELECT : reg_mux_select[addr_port*INPUT_W +: INPUT_W]
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<= m_ctrlport_req_data[0 +: INPUT_W];
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endcase
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end
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end
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end
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//---------------------------------------------------------------------------
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// User Logic
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//---------------------------------------------------------------------------
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wire [NUM_OUTPUTS*CHDR_W-1:0] tdata_demux [NUM_INPUTS-1:0];
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wire [NUM_OUTPUTS-1:0] tlast_demux [NUM_INPUTS-1:0];
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wire [NUM_OUTPUTS-1:0] tvalid_demux [NUM_INPUTS-1:0];
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wire [NUM_OUTPUTS-1:0] tready_demux [NUM_INPUTS-1:0];
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wire [NUM_INPUTS*CHDR_W-1:0] tdata_mux [NUM_OUTPUTS-1:0];
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wire [NUM_INPUTS-1:0] tlast_mux [NUM_OUTPUTS-1:0];
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wire [NUM_INPUTS-1:0] tvalid_mux [NUM_OUTPUTS-1:0];
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wire [NUM_INPUTS-1:0] tready_mux [NUM_OUTPUTS-1:0];
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generate
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genvar in_m;
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genvar out_m;
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for (in_m = 0; in_m < NUM_INPUTS; in_m = in_m + 1) begin : gen_medium_in
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for (out_m = 0; out_m < NUM_OUTPUTS; out_m = out_m + 1) begin : gen_medium_out
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assign tdata_mux[out_m][in_m*CHDR_W +: CHDR_W]
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= tdata_demux[in_m][out_m*CHDR_W +: CHDR_W];
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assign tlast_mux[out_m][in_m] = tlast_demux[in_m][out_m];
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assign tvalid_mux[out_m][in_m] = tvalid_demux[in_m][out_m];
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assign tready_demux[in_m][out_m] = tready_mux[out_m][in_m];
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end
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end
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genvar in;
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if (NUM_OUTPUTS < 2) begin : gen_static_in
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for (in = 0; in < NUM_INPUTS; in = in + 1) begin : gen_static_in_loop
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assign tdata_demux[in] = m_in_chdr_tdata[in*CHDR_W +: CHDR_W];
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assign tlast_demux[in] = m_in_chdr_tlast[in];
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assign tvalid_demux[in] = m_in_chdr_tvalid[in];
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assign m_in_chdr_tready[in] = tready_demux[in];
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end
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end else begin : gen_demux
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for (in = 0; in < NUM_INPUTS; in = in + 1) begin : gen_demux_loop
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axi_demux #(
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.WIDTH(CHDR_W),
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.SIZE(NUM_OUTPUTS)
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) axi_demux_i (
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.clk(axis_chdr_clk),
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.reset(axis_chdr_rst),
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.clear(1'b0),
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.header(),
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.dest(reg_demux_select[in*OUTPUT_W +: OUTPUT_W]),
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.i_tdata(m_in_chdr_tdata[in*CHDR_W +: CHDR_W]),
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.i_tlast(m_in_chdr_tlast[in]),
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.i_tvalid(m_in_chdr_tvalid[in]),
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.i_tready(m_in_chdr_tready[in]),
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.o_tdata(tdata_demux[in]),
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.o_tlast(tlast_demux[in]),
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.o_tvalid(tvalid_demux[in]),
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.o_tready(tready_demux[in])
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);
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end
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end
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genvar out;
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if (NUM_INPUTS < 2) begin : gen_static_out
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for (out = 0; out < NUM_OUTPUTS; out = out + 1) begin : gen_static_out_loop
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assign s_out_chdr_tdata[out*CHDR_W +: CHDR_W] = tdata_mux[out];
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assign s_out_chdr_tlast[out] = tlast_mux[out];
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assign s_out_chdr_tvalid[out] = tvalid_mux[out];
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assign tready_mux[out] = s_out_chdr_tready[out];
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end
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end else begin : gen_mux
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for (out = 0; out < NUM_OUTPUTS; out = out + 1) begin : gen_mux_loop
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axi_mux_select #(
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.WIDTH(CHDR_W),
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.SWITCH_ON_LAST(1'b1),
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.SIZE(NUM_INPUTS)
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) axi_mux_select_i (
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.clk(axis_chdr_clk),
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.reset(axis_chdr_rst),
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.clear(1'b0),
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.select(reg_mux_select[out*INPUT_W +: INPUT_W]),
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.i_tdata(tdata_mux[out]),
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.i_tlast(tlast_mux[out]),
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.i_tvalid(tvalid_mux[out]),
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.i_tready(tready_mux[out]),
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.o_tdata(s_out_chdr_tdata[out*CHDR_W +: CHDR_W]),
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.o_tlast(s_out_chdr_tlast[out]),
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.o_tvalid(s_out_chdr_tvalid[out]),
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.o_tready(s_out_chdr_tready[out])
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);
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end
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end
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endgenerate
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endmodule // rfnoc_block_switchboard
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`default_nettype wire
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