Max Köhler e9700b2081 fpga: x4xx: add option for incremental Vivado build ...

So far only the implementation after opt_run is affected by the changes.


Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6

2024-03-12 16:03:23 -05:00

..

check_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

dmd_design_build.tcl

fpga: tools: Lattice build flow clean-up

2022-08-03 14:28:21 -05:00

git-hash.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ise_jtag_program.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_modelsim.sh

fpga: tools: Detect assertions in ModelSim simulation

2021-06-17 08:16:59 -05:00

launch_vivado.py

fpga: tools: Spruce up launch_vivado.py

2023-12-13 17:28:09 -06:00

launch_vivado.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_vlint.sh

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

setupenv_base.sh

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

shared-ip-loc-manage.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_check_syntax.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_gen_ip_makefile.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_gen_part_id.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_generate_bd.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_hls_ip.tcl

fpga: hls: Add version to generated HLS IP

2022-01-13 14:33:59 -06:00

viv_generate_ip.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_patch_ip.tcl

fpga: tools: Add ability to patch IP during generation

2021-06-03 10:22:04 -05:00

viv_hardware_utils.tcl

fpga: Fix Vivado version check in viv_hardware_utils

2022-09-08 11:53:44 -05:00

viv_ip_retarget_subcores.py

mpm/fpga: x4xx: Major updates in preparation for future devices

2023-05-23 09:06:17 +02:00

viv_ip_utils.tcl

fpga: tools: viv_ip_utils to update hdl_sources.tcl

2024-03-08 08:23:49 -06:00

viv_ip_xci_editor.py

fpga: tools: Allow IP renaming with viv_ip_xci_editor.py

2022-08-25 13:55:30 -05:00

viv_sim_project.tcl

fpga: tools: Add UHD_FPGA_DIR definition to synthesis

2021-09-08 08:36:05 -05:00

viv_strategies.tcl

fpga: x4xx: add option for incremental Vivado build

2024-03-12 16:03:23 -05:00

viv_synth.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_utils.tcl

fpga: tools: Detect check_timing issues during build

2022-11-18 14:53:41 -06:00

xil_bitfile_parser.py

fpga: Fix Xilinx bitfile parser for Python 3

2021-08-24 09:45:36 -05:00