Wade Fife 2612487d43 fpga: n3xx: Add CE clock ...

Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.


Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1

2023-10-18 22:23:55 -05:00

..

common

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

mg

fpga: n3xx: Add CE clock

2023-10-18 22:23:55 -05:00

rh

fpga: n3xx: Add CE clock

2023-10-18 22:23:55 -05:00