Andrew Moch
e008853357
(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
and an AxiLiteBfm class.
Important Methods
a. wr - performs non-blocking write and checks for expected response
b. wr_block - performs a blocking write and provides response
c. rd - performs a non-blocking read and checks for expected response
d. rd_block - persforms a blocking read and provides response
The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods. When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.
Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a
42 lines
1.1 KiB
Makefile
42 lines
1.1 KiB
Makefile
#
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# Copyright 2019 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Dependencies for AXI BFMS
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##################################################
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SIM_RFNOC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/, \
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axi4lite_sv/PkgAxiLite.sv \
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axi4lite_sv/AxiLiteIf.sv \
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))
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##################################################
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# Simulation Libraries/Headers for AXI based interfaces
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##################################################
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SIM_RFNOC_SRCS += $(abspath $(addprefix $(BASE_DIR)/../sim/rfnoc/, \
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PkgTestExec.sv \
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test_exec.svh \
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sim_clock_gen.sv \
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PkgAxiStreamBfm.sv \
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PkgAxiLiteBfm.sv \
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PkgChdrData.sv \
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PkgChdrUtils.sv \
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PkgChdrBfm.sv \
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PkgAxisCtrlBfm.sv \
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PkgRfnocItemUtils.sv \
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PkgCtrlIfaceBfm.sv \
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PkgChdrIfaceBfm.sv \
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PkgRfnocBlockCtrlBfm.sv \
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))
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##################################################
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# Proto-RFNoC simlib still used in some places
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##################################################
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SIM_PROTORFNOC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sim/rfnoc/, \
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sim_rfnoc_lib.svh \
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))
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