Both files are a UHD 3 remnant and potentially confusing for UHD 4 codebase readers. Original-commit: b29af0ea0d340f37628f65e7b739fa1865d212a9
48 lines
1.3 KiB
Makefile
48 lines
1.3 KiB
Makefile
#
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# Copyright 2015 Ettus Research LLC
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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DESIGN_SRCS += $(abspath \
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../../packet_proc/arm_deframer.v \
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../../fifo/axi_mux4.v \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = arm_deframer_tb
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SIM_SRCS = $(abspath \
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$(RFNOC_SRCS) \
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arm_deframer_tb.sv \
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)
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MODELSIM_USER_DO = $(abspath wave.do)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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