7e59e9516d
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
289 lines
8.6 KiB
Verilog
289 lines
8.6 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: spi_slave
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//
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// Description:
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//
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// SPI slave for configuration CPOL = CPHA = 0.
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// Transfers 8 bit = 1 byte MSB first. Parallel data has to be
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// provided and consumed immediately when flags are asserted.
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//
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// Limitation: clk frequency <= 2*sclk frequency
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//
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// Data request from sclk domain is triggered towards the clk domain ahead of
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// time. This is due to the clock domain crossing using the synchronizer and
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// processing pipeline stages.
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//
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// The worst case propagation delay of the used synchronizer is:
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//
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// 4 'clk' clock cycles:
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// 1 clock cycle of signal propagation to synchronizer
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// (data_request_sclk assertion)
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// 1 clock cycle to capture data with instability in first stage
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// 1 clock cycle to stabilize first stage
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// 1 clock cycle to capture data in second stage
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// (data_request_clk available in 'clk' domain)
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//
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// Once synchronized in 'clk' domain, there is one additional clock cycle to
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// derive data_out_valid and data_in_required. To ensure that transmit data
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// is registered a 'clk' cycle ahead of the actual transmission we need 2
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// more 'clk' clock cycles. This ensures that transmit_word has changed and
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// is stable for at least one 'clk' cycle before 'sclk' asserts again. Any
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// additional time required externally to respond to the control port
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// requests should be considered in this crossing as well. This is a total of
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// 7 clock cycles (+ctrlport response margin) @ clk domain. The minimum
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// required time in sclk domain to issue the request is calculated based on
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// the clock frequencies.
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//
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// Parameters:
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//
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// CLK_FREQUENCY : Frequency of "clk"
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// SPI_FREQUENCY : Frequency of "sclk"
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//
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`default_nettype none
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module spi_slave #(
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parameter CLK_FREQUENCY = 50000000,
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parameter SPI_FREQUENCY = 10000000
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) (
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//---------------------------------------------------------------
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// SPI Interface
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//---------------------------------------------------------------
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input wire sclk,
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input wire cs_n,
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input wire mosi,
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output wire miso,
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//---------------------------------------------------------------
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// Parallel Interface
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//---------------------------------------------------------------
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input wire clk,
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input wire rst,
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output reg data_in_required,
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input wire data_in_valid,
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input wire [7:0] data_in,
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output reg data_out_valid,
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output reg [7:0] data_out,
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output wire active
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);
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wire [0:0] data_request_clk;
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wire [0:0] reception_complete_clk;
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//---------------------------------------------------------------
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// SPI Receiver @ sclk
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//---------------------------------------------------------------
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reg [7:0] receiver_reg;
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reg [2:0] current_bit_index;
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reg reception_complete_sclk = 1'b0;
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reg [7:0] received_word;
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always @(posedge sclk or posedge cs_n) begin
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// Reset logic on positive cs_n edge = slave idle
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if (cs_n) begin
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receiver_reg <= 8'b0;
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end
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// Rising edge of sclk
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else begin
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// Capture bits into shift register MSBs first
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receiver_reg <= {receiver_reg[6:0], mosi};
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end
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end
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// Reset with cs_n might occur too early during clk sync.
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// Reset half way through the reception.
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always @(posedge sclk) begin
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// Complete word was received
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if (current_bit_index == 7) begin
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reception_complete_sclk <= 1'b1;
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received_word <= {receiver_reg[6:0], mosi};
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// Reset after half transaction
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end else if (current_bit_index == 3) begin
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reception_complete_sclk <= 1'b0;
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end
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end
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//---------------------------------------------------------------
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// Handover of data sclk -> clk
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//---------------------------------------------------------------
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synchronizer #(
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.WIDTH (1),
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.STAGES (2),
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.INITIAL_VAL (1'b0),
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.FALSE_PATH_TO_IN (1)
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) data_sync_inst (
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.clk (clk),
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.rst (1'b0),
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.in (reception_complete_sclk),
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.out (reception_complete_clk)
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);
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//---------------------------------------------------------------
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// Parallel interface data output @ clk
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//---------------------------------------------------------------
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reg reception_complete_clk_delayed = 1'b0;
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// Propagate toggling signal without reset to ensure stability on reset
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always @(posedge clk) begin
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// Capture last state of reception
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reception_complete_clk_delayed <= reception_complete_clk;
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end
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// Derive data and control signal
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always @(posedge clk) begin
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if (rst) begin
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data_out_valid <= 1'b0;
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data_out <= 8'b0;
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end
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else begin
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// Default assignment
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data_out_valid <= 1'b0;
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// Provide data to output on rising_edge
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if (reception_complete_clk & ~reception_complete_clk_delayed) begin
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// Data can simply be captured as the reception complete signal
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// indicates stable values in received_word.
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data_out <= received_word;
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data_out_valid <= 1'b1;
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end
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end
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end
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//---------------------------------------------------------------
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// SPI Transmitter @ sclk
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//---------------------------------------------------------------
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// Data request calculation:
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// SCLK_CYCLES_DURING_DATA_REQ = 8 clk period / sclk period
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// Clock periods are expressed by reciprocal of frequencies.
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// Term "+CLK_FREQUENCY-1" is used to round up the result in integer logic.
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localparam SCLK_CYCLES_DURING_DATA_REQ = (8*SPI_FREQUENCY + CLK_FREQUENCY-1)/CLK_FREQUENCY;
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// subtract from 8 bits per transfer to get target index
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localparam DATA_REQ_BIT_INDEX = 8 - SCLK_CYCLES_DURING_DATA_REQ;
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reg [7:0] transmit_bits;
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reg [7:0] transmit_word;
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reg data_request_sclk = 1'b0;
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always @(negedge sclk or posedge cs_n) begin
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// Reset logic on positive cs_n edge = slave idle
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if (cs_n) begin
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current_bit_index <= 3'b0;
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data_request_sclk <= 1'b0;
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transmit_bits <= 8'b0;
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end
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// Falling edge of sclk
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else begin
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// Fill or move shift register for byte transmissions
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if (current_bit_index == 7) begin
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transmit_bits <= transmit_word;
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end else begin
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transmit_bits <= {transmit_bits[6:0], 1'b0};
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end
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// Update bit index
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current_bit_index <= current_bit_index + 1'b1;
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// Trigger request for new word at start of calculated index
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if (current_bit_index == DATA_REQ_BIT_INDEX-1) begin
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data_request_sclk <= 1'b1;
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// Reset after half the reception in case cs_n is not changed in between
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// two transactions.
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end else if (current_bit_index == (DATA_REQ_BIT_INDEX+4-1)%8) begin
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data_request_sclk <= 1'b0;
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end
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end
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end
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// Drive miso output with data when cs_n low
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assign miso = cs_n ? 1'bz : transmit_bits[7];
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//---------------------------------------------------------------
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// Handover of Data Request sclk -> clk
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//---------------------------------------------------------------
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synchronizer #(
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.WIDTH (1),
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.STAGES (2),
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.INITIAL_VAL (1'b0),
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.FALSE_PATH_TO_IN (1)
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) request_sync_inst (
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.clk (clk),
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.rst (rst),
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.in (data_request_sclk),
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.out (data_request_clk)
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);
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//---------------------------------------------------------------
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// Parallel Interface Data Input Control
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//---------------------------------------------------------------
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reg data_request_clk_delayed;
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always @(posedge clk) begin
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if (rst) begin
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data_request_clk_delayed <= 1'b0;
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data_in_required <= 1'b0;
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transmit_word <= 8'b0;
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end
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else begin
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// Default assignment
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data_in_required <= 1'b0;
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// Capture last state of data request
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data_request_clk_delayed <= data_request_clk;
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// Request data from input
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if (~data_request_clk_delayed & data_request_clk) begin
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data_in_required <= 1'b1;
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end
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// Capture new data if valid data available, 0 otherwise.
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if (data_in_required) begin
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if (data_in_valid) begin
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transmit_word <= data_in;
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end else begin
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transmit_word <= 8'b0;
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end
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end
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end
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end
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//---------------------------------------------------------------
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// Chip Select
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//---------------------------------------------------------------
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// Driven as active signal in parallel clock domain
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wire cs_n_clk;
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assign active = ~cs_n_clk;
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synchronizer #(
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.WIDTH (1),
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.STAGES (2),
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.INITIAL_VAL (1'b1),
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.FALSE_PATH_TO_IN (1)
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) active_sync_inst (
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.clk (clk),
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.rst (rst),
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.in (cs_n),
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.out (cs_n_clk)
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);
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endmodule
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`default_nettype wire
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