Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
423 lines
20 KiB
Verilog
423 lines
20 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: e31x_dram
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//
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// Description:
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//
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// Includes the AXI interconnect and DRAM IP to allow two AXI ports to share
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// the DRAM on E31x devices.
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//
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// Two configurations are currently supported, as shown below.
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//
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// AXI_DWIDTH NUM_PORTS dram_clk
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// ---------------------------------------
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// 128 1 100 MHz (ui_clk)
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// 64 2 200 MHz (clk200)
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//
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// Parameters:
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//
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// AXI_DWIDTH : Width of the dram_axi_* data bus. Can be 64 or 128-bit.
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// NUM_PORTS : Number of AXI ports to make available through the dram_axi_*
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// bus. Can be 1 or 2.
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//
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module e31x_dram #(
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parameter AXI_DWIDTH = 64,
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parameter NUM_PORTS = 2
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) (
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// Asynchronous reset for DDR3 controller
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input wire sys_rst,
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// Clock for DDR3 controller
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input wire ddr3_sys_clk,
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// 200 MHz clock
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input wire clk200,
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input wire clk200_rst,
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//---------------------------------------------------------------------------
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// DRAM Chip Interface
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//---------------------------------------------------------------------------
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output wire [14:0] ddr3_addr,
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output wire [2:0] ddr3_ba,
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output wire ddr3_cas_n,
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output wire [0:0] ddr3_ck_n,
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output wire [0:0] ddr3_ck_p,
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output wire [0:0] ddr3_cke,
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output wire ddr3_ras_n,
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output wire ddr3_reset_n,
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output wire ddr3_we_n,
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inout wire [15:0] ddr3_dq,
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inout wire [1:0] ddr3_dqs_n,
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inout wire [1:0] ddr3_dqs_p,
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output wire [1:0] ddr3_dm,
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output wire [0:0] ddr3_odt,
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//---------------------------------------------------------------------------
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// DRAM User Interfaces (Synchronous to dram_clk)
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//---------------------------------------------------------------------------
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output wire dram_clk,
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output wire dram_rst,
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input wire [ 29*NUM_PORTS-1:0] dram_axi_araddr,
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input wire [ 2*NUM_PORTS-1:0] dram_axi_arburst,
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input wire [ 4*NUM_PORTS-1:0] dram_axi_arcache,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_arid,
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input wire [ 8*NUM_PORTS-1:0] dram_axi_arlen,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_arlock,
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input wire [ 3*NUM_PORTS-1:0] dram_axi_arprot,
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input wire [ 4*NUM_PORTS-1:0] dram_axi_arqos,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_arready,
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input wire [ 4*NUM_PORTS-1:0] dram_axi_arregion,
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input wire [ 3*NUM_PORTS-1:0] dram_axi_arsize,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_arvalid,
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input wire [ 29*NUM_PORTS-1:0] dram_axi_awaddr,
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input wire [ 2*NUM_PORTS-1:0] dram_axi_awburst,
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input wire [ 4*NUM_PORTS-1:0] dram_axi_awcache,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_awid,
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input wire [ 8*NUM_PORTS-1:0] dram_axi_awlen,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_awlock,
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input wire [ 3*NUM_PORTS-1:0] dram_axi_awprot,
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input wire [ 4*NUM_PORTS-1:0] dram_axi_awqos,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_awready,
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input wire [ 4*NUM_PORTS-1:0] dram_axi_awregion,
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input wire [ 3*NUM_PORTS-1:0] dram_axi_awsize,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_awvalid,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_bid,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_bready,
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output wire [ 2*NUM_PORTS-1:0] dram_axi_bresp,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_bvalid,
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output wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_rdata,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_rid,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_rlast,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_rready,
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output wire [ 2*NUM_PORTS-1:0] dram_axi_rresp,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_rvalid,
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input wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_wdata,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_wlast,
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output wire [ 1*NUM_PORTS-1:0] dram_axi_wready,
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input wire [AXI_DWIDTH/8*NUM_PORTS-1:0] dram_axi_wstrb,
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input wire [ 1*NUM_PORTS-1:0] dram_axi_wvalid
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);
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//---------------------------------------------------------------------------
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// Assertions
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//---------------------------------------------------------------------------
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if (!(
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(NUM_PORTS == 1 && AXI_DWIDTH == 128) ||
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(NUM_PORTS == 2 && AXI_DWIDTH == 64)
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)) begin : check_parameters
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ERROR_Unsupported_combination_of_parameters_on_e31x_dram();
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end
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//---------------------------------------------------------------------------
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// AXI Interconnect
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//---------------------------------------------------------------------------
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wire ui_clk;
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wire ui_rst;
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// DDR3 Memory Controller AXI Interface
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wire [11:0] ddr3_axi_awid;
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wire [28:0] ddr3_axi_awaddr;
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wire [ 7:0] ddr3_axi_awlen;
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wire [ 2:0] ddr3_axi_awsize;
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wire [ 1:0] ddr3_axi_awburst;
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wire [ 0:0] ddr3_axi_awlock;
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wire [ 3:0] ddr3_axi_awcache;
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wire [ 2:0] ddr3_axi_awprot;
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wire [ 3:0] ddr3_axi_awqos;
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wire ddr3_axi_awvalid;
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wire ddr3_axi_awready;
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wire [127:0] ddr3_axi_wdata;
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wire [ 15:0] ddr3_axi_wstrb;
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wire ddr3_axi_wlast;
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wire ddr3_axi_wvalid;
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wire ddr3_axi_wready;
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wire [11:0] ddr3_axi_bid;
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wire [ 1:0] ddr3_axi_bresp;
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wire ddr3_axi_bvalid;
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wire ddr3_axi_bready;
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wire [11:0] ddr3_axi_arid;
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wire [28:0] ddr3_axi_araddr;
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wire [ 7:0] ddr3_axi_arlen;
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wire [ 2:0] ddr3_axi_arsize;
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wire [ 1:0] ddr3_axi_arburst;
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wire [ 0:0] ddr3_axi_arlock;
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wire [ 3:0] ddr3_axi_arcache;
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wire [ 2:0] ddr3_axi_arprot;
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wire [ 3:0] ddr3_axi_arqos;
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wire ddr3_axi_arvalid;
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wire ddr3_axi_arready;
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wire [ 11:0] ddr3_axi_rid;
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wire [127:0] ddr3_axi_rdata;
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wire [ 1:0] ddr3_axi_rresp;
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wire ddr3_axi_rlast;
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wire ddr3_axi_rvalid;
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wire ddr3_axi_rready;
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if (NUM_PORTS == 1 && AXI_DWIDTH == 128) begin : gen_single_port
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assign dram_clk = ui_clk;
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assign dram_rst = ui_rst;
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assign ddr3_axi_awid = dram_axi_awid;
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assign ddr3_axi_awaddr = dram_axi_awaddr;
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assign ddr3_axi_awlen = dram_axi_awlen;
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assign ddr3_axi_awsize = dram_axi_awsize;
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assign ddr3_axi_awburst = dram_axi_awburst;
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assign ddr3_axi_awlock = dram_axi_awlock;
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assign ddr3_axi_awcache = dram_axi_awcache;
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assign ddr3_axi_awprot = dram_axi_awprot;
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assign ddr3_axi_awqos = dram_axi_awqos;
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assign ddr3_axi_awvalid = dram_axi_awvalid;
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assign dram_axi_awready = ddr3_axi_awready;
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assign ddr3_axi_wdata = dram_axi_wdata;
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assign ddr3_axi_wstrb = dram_axi_wstrb;
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assign ddr3_axi_wlast = dram_axi_wlast;
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assign ddr3_axi_wvalid = dram_axi_wvalid;
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assign dram_axi_wready = ddr3_axi_wready;
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assign dram_axi_bid = ddr3_axi_bid;
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assign dram_axi_bresp = ddr3_axi_bresp;
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assign dram_axi_bvalid = ddr3_axi_bvalid;
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assign ddr3_axi_bready = dram_axi_bready;
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assign ddr3_axi_arid = dram_axi_arid;
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assign ddr3_axi_araddr = dram_axi_araddr;
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assign ddr3_axi_arlen = dram_axi_arlen;
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assign ddr3_axi_arsize = dram_axi_arsize;
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assign ddr3_axi_arburst = dram_axi_arburst;
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assign ddr3_axi_arlock = dram_axi_arlock;
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assign ddr3_axi_arcache = dram_axi_arcache;
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assign ddr3_axi_arprot = dram_axi_arprot;
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assign ddr3_axi_arqos = dram_axi_arqos;
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assign ddr3_axi_arvalid = dram_axi_arvalid;
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assign dram_axi_arready = ddr3_axi_arready;
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assign dram_axi_rid = ddr3_axi_rid;
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assign dram_axi_rdata = ddr3_axi_rdata;
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assign dram_axi_rresp = ddr3_axi_rresp;
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assign dram_axi_rlast = ddr3_axi_rlast;
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assign dram_axi_rvalid = ddr3_axi_rvalid;
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assign ddr3_axi_rready = dram_axi_rready;
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end else if (NUM_PORTS == 2 && AXI_DWIDTH == 64) begin : gen_dual_port
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assign dram_clk = clk200;
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assign dram_rst = clk200_rst;
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axi_inter_2x64_128_bd axi_inter_2x64_128_bd_i (
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.M00_AXI_ACLK (ui_clk ),
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.M00_AXI_ARESETN (~ui_rst ),
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.M00_AXI_araddr (ddr3_axi_araddr ),
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.M00_AXI_arburst (ddr3_axi_arburst ),
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.M00_AXI_arcache (ddr3_axi_arcache ),
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.M00_AXI_arid (ddr3_axi_arid ),
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.M00_AXI_arlen (ddr3_axi_arlen ),
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.M00_AXI_arlock (ddr3_axi_arlock ),
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.M00_AXI_arprot (ddr3_axi_arprot ),
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.M00_AXI_arqos (ddr3_axi_arqos ),
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.M00_AXI_arready (ddr3_axi_arready ),
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.M00_AXI_arregion( ),
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.M00_AXI_arsize (ddr3_axi_arsize ),
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.M00_AXI_arvalid (ddr3_axi_arvalid ),
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.M00_AXI_awaddr (ddr3_axi_awaddr ),
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.M00_AXI_awburst (ddr3_axi_awburst ),
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.M00_AXI_awcache (ddr3_axi_awcache ),
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.M00_AXI_awid (ddr3_axi_awid ),
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.M00_AXI_awlen (ddr3_axi_awlen ),
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.M00_AXI_awlock (ddr3_axi_awlock ),
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.M00_AXI_awprot (ddr3_axi_awprot ),
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.M00_AXI_awqos (ddr3_axi_awqos ),
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.M00_AXI_awready (ddr3_axi_awready ),
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.M00_AXI_awregion( ),
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.M00_AXI_awsize (ddr3_axi_awsize ),
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.M00_AXI_awvalid (ddr3_axi_awvalid ),
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.M00_AXI_bid (ddr3_axi_bid ),
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.M00_AXI_bready (ddr3_axi_bready ),
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.M00_AXI_bresp (ddr3_axi_bresp ),
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.M00_AXI_bvalid (ddr3_axi_bvalid ),
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.M00_AXI_rdata (ddr3_axi_rdata ),
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.M00_AXI_rid (ddr3_axi_rid ),
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.M00_AXI_rlast (ddr3_axi_rlast ),
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.M00_AXI_rready (ddr3_axi_rready ),
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.M00_AXI_rresp (ddr3_axi_rresp ),
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.M00_AXI_rvalid (ddr3_axi_rvalid ),
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.M00_AXI_wdata (ddr3_axi_wdata ),
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.M00_AXI_wlast (ddr3_axi_wlast ),
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.M00_AXI_wready (ddr3_axi_wready ),
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.M00_AXI_wstrb (ddr3_axi_wstrb ),
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.M00_AXI_wvalid (ddr3_axi_wvalid ),
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.S00_AXI_ACLK (dram_clk ),
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.S00_AXI_ARESETN (~dram_rst ),
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.S00_AXI_araddr (dram_axi_araddr [29*0 +: 29]),
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.S00_AXI_arburst (dram_axi_arburst [ 2*0 +: 2]),
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.S00_AXI_arcache (dram_axi_arcache [ 4*0 +: 4]),
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.S00_AXI_arid (dram_axi_arid [ 1*0 +: 1]),
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.S00_AXI_arlen (dram_axi_arlen [ 8*0 +: 8]),
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.S00_AXI_arlock (dram_axi_arlock [ 1*0 +: 1]),
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.S00_AXI_arprot (dram_axi_arprot [ 3*0 +: 3]),
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.S00_AXI_arqos (dram_axi_arqos [ 4*0 +: 4]),
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.S00_AXI_arready (dram_axi_arready [ 1*0 +: 1]),
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.S00_AXI_arregion(dram_axi_arregion [ 4*0 +: 4]),
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.S00_AXI_arsize (dram_axi_arsize [ 3*0 +: 3]),
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.S00_AXI_arvalid (dram_axi_arvalid [ 1*0 +: 1]),
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.S00_AXI_awaddr (dram_axi_awaddr [29*0 +: 29]),
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.S00_AXI_awburst (dram_axi_awburst [ 2*0 +: 2]),
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.S00_AXI_awcache (dram_axi_awcache [ 4*0 +: 4]),
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.S00_AXI_awid (dram_axi_awid [ 1*0 +: 1]),
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.S00_AXI_awlen (dram_axi_awlen [ 8*0 +: 8]),
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.S00_AXI_awlock (dram_axi_awlock [ 1*0 +: 1]),
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.S00_AXI_awprot (dram_axi_awprot [ 3*0 +: 3]),
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.S00_AXI_awqos (dram_axi_awqos [ 4*0 +: 4]),
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.S00_AXI_awready (dram_axi_awready [ 1*0 +: 1]),
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.S00_AXI_awregion(dram_axi_awregion [ 4*0 +: 4]),
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.S00_AXI_awsize (dram_axi_awsize [ 3*0 +: 3]),
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.S00_AXI_awvalid (dram_axi_awvalid [ 1*0 +: 1]),
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.S00_AXI_bid (dram_axi_bid [ 1*0 +: 1]),
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.S00_AXI_bready (dram_axi_bready [ 1*0 +: 1]),
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.S00_AXI_bresp (dram_axi_bresp [ 2*0 +: 2]),
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.S00_AXI_bvalid (dram_axi_bvalid [ 1*0 +: 1]),
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.S00_AXI_rdata (dram_axi_rdata [64*0 +: 64]),
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.S00_AXI_rid (dram_axi_rid [ 1*0 +: 1]),
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.S00_AXI_rlast (dram_axi_rlast [ 1*0 +: 1]),
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.S00_AXI_rready (dram_axi_rready [ 1*0 +: 1]),
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.S00_AXI_rresp (dram_axi_rresp [ 2*0 +: 2]),
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.S00_AXI_rvalid (dram_axi_rvalid [ 1*0 +: 1]),
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.S00_AXI_wdata (dram_axi_wdata [64*0 +: 64]),
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.S00_AXI_wlast (dram_axi_wlast [ 1*0 +: 1]),
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.S00_AXI_wready (dram_axi_wready [ 1*0 +: 1]),
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.S00_AXI_wstrb (dram_axi_wstrb [ 8*0 +: 8]),
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.S00_AXI_wvalid (dram_axi_wvalid [ 1*0 +: 1]),
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.S01_AXI_ACLK (dram_clk ),
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.S01_AXI_ARESETN (~dram_rst ),
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.S01_AXI_araddr (dram_axi_araddr [29*1 +: 29]),
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.S01_AXI_arburst (dram_axi_arburst [ 2*1 +: 2]),
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.S01_AXI_arcache (dram_axi_arcache [ 4*1 +: 4]),
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.S01_AXI_arid (dram_axi_arid [ 1*1 +: 1]),
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.S01_AXI_arlen (dram_axi_arlen [ 8*1 +: 8]),
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.S01_AXI_arlock (dram_axi_arlock [ 1*1 +: 1]),
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.S01_AXI_arprot (dram_axi_arprot [ 3*1 +: 3]),
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.S01_AXI_arqos (dram_axi_arqos [ 4*1 +: 4]),
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.S01_AXI_arready (dram_axi_arready [ 1*1 +: 1]),
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.S01_AXI_arregion(dram_axi_arregion [ 4*1 +: 4]),
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.S01_AXI_arsize (dram_axi_arsize [ 3*1 +: 3]),
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.S01_AXI_arvalid (dram_axi_arvalid [ 1*1 +: 1]),
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.S01_AXI_awaddr (dram_axi_awaddr [29*1 +: 29]),
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.S01_AXI_awburst (dram_axi_awburst [ 2*1 +: 2]),
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.S01_AXI_awcache (dram_axi_awcache [ 4*1 +: 4]),
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.S01_AXI_awid (dram_axi_awid [ 1*1 +: 1]),
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.S01_AXI_awlen (dram_axi_awlen [ 8*1 +: 8]),
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.S01_AXI_awlock (dram_axi_awlock [ 1*1 +: 1]),
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.S01_AXI_awprot (dram_axi_awprot [ 3*1 +: 3]),
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.S01_AXI_awqos (dram_axi_awqos [ 4*1 +: 4]),
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.S01_AXI_awready (dram_axi_awready [ 1*1 +: 1]),
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.S01_AXI_awregion(dram_axi_awregion [ 4*1 +: 4]),
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.S01_AXI_awsize (dram_axi_awsize [ 3*1 +: 3]),
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.S01_AXI_awvalid (dram_axi_awvalid [ 1*1 +: 1]),
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.S01_AXI_bid (dram_axi_bid [ 1*1 +: 1]),
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.S01_AXI_bready (dram_axi_bready [ 1*1 +: 1]),
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.S01_AXI_bresp (dram_axi_bresp [ 2*1 +: 2]),
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.S01_AXI_bvalid (dram_axi_bvalid [ 1*1 +: 1]),
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.S01_AXI_rdata (dram_axi_rdata [64*1 +: 64]),
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.S01_AXI_rid (dram_axi_rid [ 1*1 +: 1]),
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.S01_AXI_rlast (dram_axi_rlast [ 1*1 +: 1]),
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.S01_AXI_rready (dram_axi_rready [ 1*1 +: 1]),
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.S01_AXI_rresp (dram_axi_rresp [ 2*1 +: 2]),
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.S01_AXI_rvalid (dram_axi_rvalid [ 1*1 +: 1]),
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.S01_AXI_wdata (dram_axi_wdata [64*1 +: 64]),
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.S01_AXI_wlast (dram_axi_wlast [ 1*1 +: 1]),
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.S01_AXI_wready (dram_axi_wready [ 1*1 +: 1]),
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.S01_AXI_wstrb (dram_axi_wstrb [ 8*1 +: 8]),
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.S01_AXI_wvalid (dram_axi_wvalid [ 1*1 +: 1])
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);
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end
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//---------------------------------------------------------------------------
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// DDR3 Memory Controller
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//---------------------------------------------------------------------------
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ddr3_16bit ddr3_16bit_i (
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// Memory interface ports
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.ddr3_addr (ddr3_addr ), // output [14:0] ddr3_addr
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.ddr3_ba (ddr3_ba ), // output [2:0] ddr3_ba
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.ddr3_cas_n (ddr3_cas_n ), // output ddr3_cas_n
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.ddr3_ck_n (ddr3_ck_n ), // output [0:0] ddr3_ck_n
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.ddr3_ck_p (ddr3_ck_p ), // output [0:0] ddr3_ck_p
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.ddr3_cke (ddr3_cke ), // output [0:0] ddr3_cke
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.ddr3_ras_n (ddr3_ras_n ), // output ddr3_ras_n
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.ddr3_reset_n (ddr3_reset_n ), // output ddr3_reset_n
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.ddr3_we_n (ddr3_we_n ), // output ddr3_we_n
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.ddr3_dq (ddr3_dq ), // inout [15:0] ddr3_dq
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.ddr3_dqs_n (ddr3_dqs_n ), // inout [1:0] ddr3_dqs_n
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.ddr3_dqs_p (ddr3_dqs_p ), // inout [1:0] ddr3_dqs_p
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.ddr3_dm (ddr3_dm ), // output [1:0] ddr3_dm
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.ddr3_odt (ddr3_odt ), // output [0:0] ddr3_odt
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// Application interface ports
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.init_calib_complete( ), // output init_calib_complete
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.device_temp ( ), // output [11:0] device_temp;
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.ui_clk (ui_clk ), // output ui_clk
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.ui_clk_sync_rst (ui_rst ), // output ui_clk_sync_rst
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.mmcm_locked ( ), // output mmcm_locked
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.app_sr_req (1'b0 ), // input app_sr_req
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.app_ref_req (1'b0 ), // input app_ref_req
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.app_zq_req (1'b0 ), // input app_zq_req
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.app_sr_active ( ), // output app_sr_active
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.app_ref_ack ( ), // output app_ref_ack
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.app_zq_ack ( ), // output app_zq_ack
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// AXI Interface Reset
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.aresetn (~ui_rst ), // input aresetn
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// Slave Interface Write Address Ports
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.s_axi_awid (ddr3_axi_awid ), // input [11:0] s_axi_awid
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.s_axi_awaddr (ddr3_axi_awaddr ), // input [28:0] s_axi_awaddr
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.s_axi_awlen (ddr3_axi_awlen ), // input [7:0] s_axi_awlen
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.s_axi_awsize (ddr3_axi_awsize ), // input [2:0] s_axi_awsize
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.s_axi_awburst (ddr3_axi_awburst), // input [1:0] s_axi_awburst
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.s_axi_awlock (ddr3_axi_awlock ), // input [0:0] s_axi_awlock
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.s_axi_awcache (ddr3_axi_awcache), // input [3:0] s_axi_awcache
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.s_axi_awprot (ddr3_axi_awprot ), // input [2:0] s_axi_awprot
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.s_axi_awqos (ddr3_axi_awqos ), // input [3:0] s_axi_awqos
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.s_axi_awvalid (ddr3_axi_awvalid), // input s_axi_awvalid
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.s_axi_awready (ddr3_axi_awready), // output s_axi_awready
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// Slave Interface Write Data Ports
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.s_axi_wdata (ddr3_axi_wdata ), // input [127:0] s_axi_wdata
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.s_axi_wstrb (ddr3_axi_wstrb ), // input [15:0] s_axi_wstrb
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.s_axi_wlast (ddr3_axi_wlast ), // input s_axi_wlast
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.s_axi_wvalid (ddr3_axi_wvalid ), // input s_axi_wvalid
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.s_axi_wready (ddr3_axi_wready ), // output s_axi_wready
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// Slave Interface Write Response Ports
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.s_axi_bid (ddr3_axi_bid ), // output [11:0] s_axi_bid
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|
.s_axi_bresp (ddr3_axi_bresp ), // output [1:0] s_axi_bresp
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.s_axi_bvalid (ddr3_axi_bvalid ), // output s_axi_bvalid
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.s_axi_bready (ddr3_axi_bready ), // input s_axi_bready
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// Slave Interface Read Address Ports
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.s_axi_arid (ddr3_axi_arid ), // input [11:0] s_axi_arid
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|
.s_axi_araddr (ddr3_axi_araddr ), // input [28:0] s_axi_araddr
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|
.s_axi_arlen (ddr3_axi_arlen ), // input [7:0] s_axi_arlen
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|
.s_axi_arsize (ddr3_axi_arsize ), // input [2:0] s_axi_arsize
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|
.s_axi_arburst (ddr3_axi_arburst), // input [1:0] s_axi_arburst
|
|
.s_axi_arlock (ddr3_axi_arlock ), // input [0:0] s_axi_arlock
|
|
.s_axi_arcache (ddr3_axi_arcache), // input [3:0] s_axi_arcache
|
|
.s_axi_arprot (ddr3_axi_arprot ), // input [2:0] s_axi_arprot
|
|
.s_axi_arqos (ddr3_axi_arqos ), // input [3:0] s_axi_arqos
|
|
.s_axi_arvalid (ddr3_axi_arvalid), // input s_axi_arvalid
|
|
.s_axi_arready (ddr3_axi_arready), // output s_axi_arready
|
|
// Slave Interface Read Data Ports
|
|
.s_axi_rid (ddr3_axi_rid ), // output [11:0] s_axi_rid
|
|
.s_axi_rdata (ddr3_axi_rdata ), // output [127:0] s_axi_rdata
|
|
.s_axi_rresp (ddr3_axi_rresp ), // output [1:0] s_axi_rresp
|
|
.s_axi_rlast (ddr3_axi_rlast ), // output s_axi_rlast
|
|
.s_axi_rvalid (ddr3_axi_rvalid ), // output s_axi_rvalid
|
|
.s_axi_rready (ddr3_axi_rready ), // input s_axi_rready
|
|
// System Clock Ports
|
|
.sys_clk_i (ddr3_sys_clk ), // input sys_clk_i
|
|
// Reference Clock Ports
|
|
.clk_ref_i (clk200 ),
|
|
.sys_rst (sys_rst ) // input sys_rst
|
|
);
|
|
|
|
endmodule
|