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Max Köhler 6bea1f8222 fpga: lib: Modify for loop to Verilog 2001 syntax 
This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).


Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a
2020-03-09 13:40:17 -05:00
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axis_ctrlport_reg.v
Merge FPGA repository back into UHD repository
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chdr_pad_packet.v
Merge FPGA repository back into UHD repository
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chdr_trim_payload.v
Merge FPGA repository back into UHD repository
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context_builder.v
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context_handler_sync.v
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context_parser.v
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ctrlport_clk_cross.v
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2020-01-28 09:35:36 -08:00
ctrlport_combiner.v
Merge FPGA repository back into UHD repository
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ctrlport_decoder_param.v
fpga: lib: Modify for loop to Verilog 2001 syntax
2020-03-09 13:40:17 -05:00
ctrlport_decoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_reg_ro.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_reg_rw.v
Merge FPGA repository back into UHD repository
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ctrlport_resp_combine.v
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2020-01-28 09:35:36 -08:00
ctrlport_splitter.v
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ctrlport_terminator.v
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ctrlport_timer.v
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ctrlport_to_settings_bus.v
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Makefile.srcs
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2020-01-28 09:35:36 -08:00
noc_shell_generic_ctrlport_pyld_chdr.v
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2020-01-28 09:35:36 -08:00
timekeeper.v
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