93 lines
3.0 KiB
Verilog
93 lines
3.0 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_gate
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//
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// Description:
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//
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// This block forwards or blocks a control-port interface request based on the
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// enable input.
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//
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module ctrlport_gate (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Control interface
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input wire enable,
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// Slave interface
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// Master interface
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output reg m_ctrlport_req_wr,
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output reg m_ctrlport_req_rd,
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output reg [19:0] m_ctrlport_req_addr,
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output reg [ 9:0] m_ctrlport_req_portid,
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output reg [15:0] m_ctrlport_req_rem_epid,
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output reg [ 9:0] m_ctrlport_req_rem_portid,
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output reg [31:0] m_ctrlport_req_data,
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output reg [ 3:0] m_ctrlport_req_byte_en,
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output reg m_ctrlport_req_has_time,
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output reg [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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`include "../core/ctrlport.vh"
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always @(posedge ctrlport_clk) begin
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// Forward all signals by default
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m_ctrlport_req_wr <= s_ctrlport_req_wr;
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m_ctrlport_req_rd <= s_ctrlport_req_rd;
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m_ctrlport_req_addr <= s_ctrlport_req_addr;
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m_ctrlport_req_portid <= s_ctrlport_req_portid;
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m_ctrlport_req_rem_epid <= s_ctrlport_req_rem_epid;
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m_ctrlport_req_rem_portid <= s_ctrlport_req_rem_portid;
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m_ctrlport_req_data <= s_ctrlport_req_data;
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m_ctrlport_req_byte_en <= s_ctrlport_req_byte_en;
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m_ctrlport_req_has_time <= s_ctrlport_req_has_time;
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m_ctrlport_req_time <= s_ctrlport_req_time;
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s_ctrlport_resp_ack <= m_ctrlport_resp_ack;
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s_ctrlport_resp_status <= m_ctrlport_resp_status;
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s_ctrlport_resp_data <= m_ctrlport_resp_data;
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// Handle reset and disabled case
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if (ctrlport_rst) begin
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m_ctrlport_req_wr <= 1'b0;
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m_ctrlport_req_rd <= 1'b0;
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s_ctrlport_resp_ack <= 1'b0;
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end else begin
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// Overwrite default assignments in case of disabled interface
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if (m_ctrlport_req_rd || m_ctrlport_req_wr) begin
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if (~enable) begin
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// Block forwarding of request
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m_ctrlport_req_wr <= 1'b0;
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m_ctrlport_req_rd <= 1'b0;
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// Issue error as response
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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end
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end
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end
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end
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endmodule
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